公开(公告)号：US20160357462A1

公开(公告)日：2016-12-08

申请号：US15096877

申请日：2016-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee Hyun Nam ,  Jaegeun Park ,  Sungyong Seo ,  Youngkwang Yoo ,  Han-Ju Lee ,  Youngjin Cho

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0685

Abstract: Disclosed is a nonvolatile memory module. The nonvolatile memory module includes at least one nonvolatile memory, a random access memory (RAM) and a device controller. Responsive to receiving a write request comprising sub-data from a host, the device controller accumulates the sub-data in the RAM and programs the accumulated sub-data in the nonvolatile memory. A size of the sub-data is smaller than a size of a default transmission unit provided from the host.

Abstract translation: 公开了一种非易失性存储器模块。 非易失性存储器模块包括至少一个非易失性存储器，随机存取存储器（RAM）和器件控制器。 响应于从主机接收到包含子数据的写入请求，设备控制器将该子数据累加在RAM中，并将累积的子数据编程在非易失性存储器中。 子数据的大小小于从主机提供的默认传输单元的大小。

公开(公告)号：US20240320173A1

公开(公告)日：2024-09-26

申请号：US18610528

申请日：2024-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngsuk Moon ,  Jaegeun Park ,  Jiwon Chang ,  Sangmuk Hwang

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F2213/28

Abstract: A storage device includes a buffer memory, a first direct memory access (DMA) circuit configured to provide data from a host to the buffer memory or data stored in the buffer memory to the host and output a first virtual address, a second DMA circuit configured to provide data read from a non-volatile memory to the buffer memory or the data stored in the buffer memory to the non-volatile memory and output a second virtual address, an address translation circuit configured to translate the first or second virtual address into a physical address when the first or second virtual address is included in a reference range and skip the translation operation when the first or second virtual address is excluded in the reference range. A buffer controller is configured to access the buffer memory based on the physical address of the first or second virtual address that is excluded.

公开(公告)号：US12013796B2

公开(公告)日：2024-06-18

申请号：US17751798

申请日：2022-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmuk Hwang ,  Jaegeun Park ,  Hojun Shim ,  Byungchul Yoo

IPC: G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1642 ,  G06F13/161 ,  G06F13/1689 ,  G06F13/28

Abstract: A storage controller includes a command manager and a direct memory access (DMA) engine. The command manager receives a first submission queue doorbell from an external device, fetches a first command including a first latency from the external device in response to the first submission queue doorbell, and determines a first timing to write a first completion into the external device based on the first latency, the first completion indicating that the first command is completely processed. The DMA engine receives a request signal requesting processing of the first command from the command manager, transfer data, which the first command requests, based on a DMA transfer in response to the request signal, and outputs a complete signal, which indicates that the first command is completely processed, to the command manager.

公开(公告)号：US11086571B2

公开(公告)日：2021-08-10

申请号：US16789526

申请日：2020-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Kim ,  Jaegeun Park ,  Youngjin Cho

IPC: G06F3/06 ,  G06F11/10 ,  G06F11/00 ,  G06F13/28 ,  G06F12/0868 ,  G06F12/0831 ,  G06F12/0879

Abstract: A read method executed by a computing system includes a processor, at least one nonvolatile memory, and at least one cache memory performing a cache function of the at least one nonvolatile memory. The method includes receiving a read request regarding a critical word from the processor. A determination is made whether a cache miss is generated, through a tag determination operation corresponding to the read request. Page data corresponding to the read request is received from the at least one nonvolatile memory in a wraparound scheme when a result of the tag determination operation indicates that the cache miss is generated. The critical word is output to the processor when the critical word of the page data is received.

公开(公告)号：US09515675B2

公开(公告)日：2016-12-06

申请号：US14593585

申请日：2015-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonsung Bae ,  Jaegeun Park ,  Kwang Hee Choi

IPC: H04L9/06 ,  H04L25/14 ,  H04L1/00 ,  H03M5/14

CPC classification number: H03M5/145 ,  H04L1/0009 ,  H04L1/0045 ,  H04L1/0071 ,  H04L9/0662 ,  H04L25/14

Abstract: Provided is an interface circuit for transmitting and receiving data according to a communication protocol. The interface circuit includes: an encoder configured to encode input data to generate transmission data; a transmitter configured to output the transmission data; a data sequence detector configured to detect whether the number of successively same logic values in a data string of the transmission data is equal to or greater than a reference succession number; and a recovery section configured to control a recovery operation with respect to the transmission data, based on a detection result of the data sequence detector. With the interface circuit, data loss is prevented and data reliability is guaranteed.

Abstract translation: 提供了一种用于根据通信协议发送和接收数据的接口电路。 接口电路包括：编码器，被配置为编码输入数据以产生传输数据; 发送器，被配置为输出所述发送数据; 数据序列检测器，被配置为检测所述发送数据的数据串中的连续相同逻辑值的数量是否等于或大于参考连续数; 以及恢复部，其被配置为基于所述数据序列检测器的检测结果来控制关于所述发送数据的恢复操作。 使用接口电路，可以防止数据丢失，保证数据的可靠性。

公开(公告)号：US09306583B2

公开(公告)日：2016-04-05

申请号：US14638363

申请日：2015-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soon Suk Hwang ,  Youngjin Cho ,  Kyuwook Han ,  Jaegeun Park

IPC: G11C7/00 ,  H03L7/08 ,  H03L7/085 ,  G11C7/22

CPC classification number: H03L7/0802 ,  G06F1/04 ,  G06F13/1689 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/085 ,  H03L2207/50 ,  Y02D10/14

Abstract: A delay locked loop (DLL) is provided. The DLL includes a delay line, a phase detector, a delay line control unit, and a DLL controller. The delay line outputs an output clock by delaying an input clock by a first time on the basis of a select value. The phase detector detects a phase of the output clock. The delay line control unit determines a select value so that the first time corresponds to n periods of the input clock on the basis of the detected phase and an initial select value. The DLL controller provides the initial select value to the delay line control unit. The DLL controller updates the initial select value according to a change of a frequency of the input clock, and to provide the updated initial select value to the delay line control unit.

Abstract translation: 提供延迟锁定环（DLL）。 DLL包括延迟线，相位检测器，延迟线控制单元和DLL控制器。 延迟线通过基于选择值第一次延迟输入时钟来输出输出时钟。 相位检测器检测输出时钟的相位。 延迟线控制单元确定选择值，使得第一时间基于检测到的相位和初始选择值对应于输入时钟的n个周期。 DLL控制器向延迟线控制单元提供初始选择值。 DLL控制器根据输入时钟频率的变化来更新初始选择值，并向延迟线控制单元提供更新的初始选择值。

公开(公告)号：US20150256187A1

公开(公告)日：2015-09-10

申请号：US14638363

申请日：2015-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOON SUK HWANG ,  Youngjin Cho ,  Kyuwook Han ,  Jaegeun Park

IPC: H03L7/08 ,  G11C7/22 ,  H03L7/085

CPC classification number: H03L7/0802 ,  G06F1/04 ,  G06F13/1689 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/085 ,  H03L2207/50 ,  Y02D10/14

Abstract: A delay locked loop (DLL) is provided. The DLL includes a delay line, a phase detector, a delay line control unit, and a DLL controller. The delay line outputs an output clock by delaying an input clock by a first time on the basis of a select value. The phase detector detects a phase of the output clock. The delay line control unit determines a select value so that the first time corresponds to n periods of the input clock on the basis of the detected phase and an initial select value. The DLL controller provides the initial select value to the delay line control unit. The DLL controller updates the initial select value according to a change of a frequency of the input clock, and to provide the updated initial select value to the delay line control unit.

Abstract translation: 提供延迟锁定环（DLL）。 DLL包括延迟线，相位检测器，延迟线控制单元和DLL控制器。 延迟线通过基于选择值第一次延迟输入时钟来输出输出时钟。 相位检测器检测输出时钟的相位。 延迟线控制单元确定选择值，使得第一时间基于检测到的相位和初始选择值对应于输入时钟的n个周期。 DLL控制器向延迟线控制单元提供初始选择值。 DLL控制器根据输入时钟频率的变化来更新初始选择值，并向延迟线控制单元提供更新的初始选择值。