公开(公告)号：US09917161B2

公开(公告)日：2018-03-13

申请号：US15238721

申请日：2016-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungwoo Song ,  Jaekyu Lee ,  Jaerok Kahng ,  YongJun Kim

IPC: H01L27/108 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/22

CPC classification number: H01L29/408 ,  H01L27/10811 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10891 ,  H01L27/228 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device includes active pillars protruding from a semiconductor substrate and spaced apart from each other in a first direction and a second direction that is perpendicular to the first direction, a word line extending in the first direction between the active pillars, a drain region disposed in an upper portion of each of the active pillars, and a separation pattern provided between the word line and the drain region. A bottom surface of the separation pattern is disposed at a lower level than a bottom surface of the drain region.

公开(公告)号：US09118010B2

公开(公告)日：2015-08-25

申请号：US14328056

申请日：2014-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun Hong ,  Jaekyu Lee ,  Yong Kwan Kim

IPC: H01L45/00 ,  H01L27/10 ,  H01L27/24 ,  H01L27/22

CPC classification number: H01L45/1683 ,  H01L27/101 ,  H01L27/224 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1273 ,  H01L45/1608 ,  H01L45/1675

Abstract: According to an example embodiment, a variable resistance memory device includes a lower electrode that includes a spacer-shaped first sub lower electrode and a second sub lower electrode covering a curved sidewall of the first sub lower electrode. The second sub lower electrode extends upward to protrude above the top of the first sub lower electrode. The lower electrode includes an upward-tapered shape.

Abstract translation: 根据示例性实施例，可变电阻存储器件包括下电极，其包括间隔物形的第一副下电极和覆盖第一副下电极的弯曲侧壁的第二副下电极。 第二副下电极向上延伸以突出在第一子下电极的顶部之上。 下电极包括向上锥形的形状。

公开(公告)号：US11653110B2

公开(公告)日：2023-05-16

申请号：US17476220

申请日：2021-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaekyu Lee ,  Heesung Shim

IPC: H04N5/353 ,  H04N5/378 ,  H04N5/374 ,  H01L27/146 ,  H04N5/369 ,  H04N5/376

CPC classification number: H04N5/3532 ,  H01L27/14612 ,  H01L27/14643 ,  H04N5/378

Abstract: An image sensor is disclosed. The image sensor includes a plurality of pixels arranged in a plurality of rows and a plurality of columns, each of the pixels including: a photodiode; a floating diffusion node configured to accumulate photocharges generated from the photodiode; a first capacitor configured to store charges according to a voltage of the floating diffusion node which is reset; a second capacitor configured to store charges according to a voltage of the floating diffusion node in which the photocharges are accumulated; a first sampling transistor connected to a first output node and configured to sample charges to the first capacitor; a second sampling transistor connected to the first output node and configured to sample charges to the second capacitor; and at least one precharge select transistor connected to the first output node and configured to reset the first output node.

公开(公告)号：US11545526B2

公开(公告)日：2023-01-03

申请号：US17386821

申请日：2021-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gwideok Ryan Lee ,  Jaekyu Lee

IPC: H01L27/30

Abstract: An image sensor includes a substrate including a first surface and a second surface, a first transmission gate electrode on the first surface of the substrate, a storage node on the first surface of the substrate and including a first storage gate electrode isolated from direct contact with the first transmission gate electrode, a dielectric layer on the first storage gate electrode, and a semiconductor layer on the dielectric layer. The image sensor may include a first cover insulating layer on the semiconductor layer and vertically overlapping the first transmission gate electrode, and an organic photoelectric conversion layer on an upper surface of the semiconductor layer and an upper surface of the first cover insulating layer.

公开(公告)号：US11025844B2

公开(公告)日：2021-06-01

申请号：US16674202

申请日：2019-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minwoong Seo ,  Seungsik Kim ,  Jungchak Ahn ,  Jaekyu Lee ,  Dongmo Im ,  Dongseok Cho

IPC: H04N5/355

Abstract: A method of driving an image sensor includes integrating an overflowed charge from a photodiode in the floating diffusion area and a dynamic range capacitor. The dynamic range capacitor is formed between the floating diffusion area and a power supply voltage. The method further includes sampling a first voltage formed in the floating diffusion area by the integrated overflowed charge, resetting the photodiode, the floating diffusion area, and the dynamic range capacitor, sampling a reset level of the reset floating diffusion area, transferring a charge accumulated in the photodiode to the floating diffusion area, and sampling a second voltage formed in the floating diffusion area.

公开(公告)号：US20240107195A1

公开(公告)日：2024-03-28

申请号：US18240483

申请日：2023-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heesung Shim ,  Seungsik Kim ,  Jaekyu Lee ,  Seunghyun Lim ,  Sungjae Jun

IPC: H04N25/771 ,  H04N23/667 ,  H04N25/531 ,  H04N25/532

CPC classification number: H04N25/771 ,  H04N23/667 ,  H04N25/531 ,  H04N25/532

Abstract: An image sensor comprising a pixel array in which a plurality of pixels are arranged and a row driver . Each of the pixel includes a photodiode, a transfer transistor for transferring photocharges of the photodiode to a floating diffusion node (FD), a conversion gain control transistor, a first source follower for amplifying and outputting the voltage of the FD to a first node, a precharge selection transistor connected between the first node and a second node, a first capacitor, a first sampling transistor connected between the second node and the first capacitor, a second capacitor, a second sampling transistor connected between the second node and the second capacitor, a second source follower for amplifying a voltage of the second node, a first selection transistor connected between the second source follower and a column line, and a second selection transistor connected between the first node and the column line.

公开(公告)号：US11750942B2

公开(公告)日：2023-09-05

申请号：US17577566

申请日：2022-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaekyu Lee

IPC: H04N25/531 ,  H04N25/75 ,  H04N25/771 ,  H01L27/146 ,  H04N25/71

CPC classification number: H04N25/531 ,  H04N25/75 ,  H04N25/771 ,  H01L27/1463 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14645 ,  H04N25/745

Abstract: An image sensor including: first and second capacitors; a first transistor between a photodiode and a floating diffusion node, and receiving a transfer signal; a second transistor between a first power terminal and the floating diffusion node and receiving a reset signal; a third transistor between a second power terminal and a first node and having a gate connected to the floating diffusion node; a fourth transistor between the first node and a column line and receiving a precharge signal; a fifth transistor between the first capacitor and a feedback node and receiving a first sampling signal; a sixth transistor between the second capacitor and feedback node and receiving a second sampling signal; a seventh transistor between the first node and feedback node and receiving a first switch signal; and an eighth transistor between the floating diffusion and feedback nodes and receiving a second switch signal.

公开(公告)号：US10763294B2

公开(公告)日：2020-09-01

申请号：US16203912

申请日：2018-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyu Lee ,  Sung In Kim ,  Byung-Joon Baek

IPC: H01L27/146 ,  H04N5/369 ,  H04N5/3745 ,  H04N5/378

Abstract: An image sensor chip may include a first sub-chip, a second sub-chip on the first sub-chip, and an interconnector between the first and second sub-chips. The first sub-chip may include a first substrate, a bottom electrode on a first region of the first substrate, and a first capacitor on the bottom electrode. The first capacitor may include a plurality of first electrodes vertically extending from a top surface of the bottom electrode, a second electrode on the first electrodes, and a first dielectric layer between the second electrode and the first electrodes. The second sub-chip may include a pixel array configured to convert incident light into an electrical signal. The pixel array may be electrically connected through the interconnector to the first capacitor.

公开(公告)号：US20190267423A1

公开(公告)日：2019-08-29

申请号：US16203912

申请日：2018-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyu Lee ,  Sung In Kim ,  Byung-Joon Baek

IPC: H01L27/146 ,  H04N5/3745 ,  H04N5/378 ,  H04N5/369

Abstract: An image sensor chip may include a first sub-chip, a second sub-chip on the first sub-chip, and an interconnector between the first and second sub-chips. The first sub-chip may include a first substrate, a bottom electrode on a first region of the first substrate, and a first capacitor on the bottom electrode. The first capacitor may include a plurality of first electrodes vertically extending from a top surface of the bottom electrode, a second electrode on the first electrodes, and a first dielectric layer between the second electrode and the first electrodes. The second sub-chip may include a pixel array configured to convert incident light into an electrical signal. The pixel array may be electrically connected through the interconnector to the first capacitor.

公开(公告)号：US10199497B2

公开(公告)日：2019-02-05

申请号：US15672767

申请日：2017-08-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wooyeong Cho ,  Jaekyu Lee

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L29/78

Abstract: A semiconductor device includes an active pillar that protrudes above a substrate, the active pillar including a pair of vertical sections and a body interconnection between the pair of vertical sections, and each of the pair of vertical sections having a channel body and a lower impurity region below the channel body, word lines coupled to respective channel bodies, and buried bit lines in contact with respective lower impurity regions, wherein the channel bodies are connected to the substrate through the body interconnection.