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    MEMORY DEVICE FOR SUPPORTING NEW COMMAND INPUT SCHEME AND METHOD OF OPERATING THE SAME
    17.
    发明申请
    MEMORY DEVICE FOR SUPPORTING NEW COMMAND INPUT SCHEME AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20220139433A1

    公开(公告)日：2022-05-05

    申请号：US17574174

    申请日：2022-01-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngcheon Kwon ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee ,  Jihyun Choi

    IPC: G11C7/22 ,  G11C7/10

    Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.

    Memory device performing configurable mode setting and method of operating the same
    19.
    发明授权
    Memory device performing configurable mode setting and method of operating the same 有权

    公开(公告)号：US11561711B2

    公开(公告)日：2023-01-24

    申请号：US17335307

    申请日：2021-06-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngcheon Kwon ,  Jaesan Kim ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee

    IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  H01L25/18

    Abstract: A memory device according to an aspect may include a memory cell array including a first bank region and a second bank region each including a plurality of banks; an operation logic including one or more first processing elements (PEs) corresponding to the first bank region and one or more second PEs corresponding to the second bank region; a control logic configured to control modes of the first bank region and the second bank region based on externally sourced setting information; first and second mode signal generators configured to control enabling the first PEs, wherein the first mode signal generator is configured to output the first mode signal to enable the first PEs and the second mode signal generator is configured to output the second mode signal to disable the second PEs responsive to the first bank region being set to an operation mode and the second bank region being set to a normal mode.

    Memory device including processing circuit, and electronic device including system on chip and memory device
    20.
    发明授权
    Memory device including processing circuit, and electronic device including system on chip and memory device 有权

    公开(公告)号：US11301399B2

    公开(公告)日：2022-04-12

    申请号：US16934497

    申请日：2020-07-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Hyuk Kwon ,  Nam Sung Kim ,  Kyomin Sohn ,  Jaeyoun Youn

    IPC: G06F13/38 ,  G06F13/16 ,  H01L25/065 ,  G11C8/10 ,  G11C7/10

    Abstract: A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.

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