公开(公告)号：US11836097B2

公开(公告)日：2023-12-05

申请号：US17229198

申请日：2021-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Won Park ,  Je-Min Ryu ,  Sang-Hoon Shin ,  Jae-Hoon Jung

IPC: G06F13/16 ,  G06F12/06 ,  G06F12/0866

CPC classification number: G06F13/1673 ,  G06F12/0607 ,  G06F12/0866 ,  G06F2212/601

Abstract: A memory device includes a first channel including a first cell array and communicating with a memory controller through a first path, a second channel including a second cell array and communicating with the memory controller through a second path, and an assignment control circuit configured to monitor memory usage of the first and second channels and further assign a storage space of a portion of the second cell array to the first channel when the memory usage of the first cell array exceeds a threshold value. Access to the storage space of the portion of the second cell array assigned to the first channel is performed through the first path.

公开(公告)号：US10410685B2

公开(公告)日：2019-09-10

申请号：US16293372

申请日：2019-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Reum Oh ,  Je-Min Ryu ,  Pavan Kumar Kasibhatla

IPC: G11C5/02 ,  G06F12/0893 ,  G11C29/12 ,  G11C29/48 ,  G11C7/10 ,  G06F12/084 ,  H01L25/18

Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.

公开(公告)号：US10331354B2

公开(公告)日：2019-06-25

申请号：US15617450

申请日：2017-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hak-Soo Yu ,  Je-Min Ryu ,  Reum Oh ,  Pavan Kumar Kasibhatla ,  Seok-In Hong

IPC: G06F3/06 ,  G11C5/02 ,  G11C5/06 ,  G11C5/04

Abstract: A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.

公开(公告)号：US09601216B2

公开(公告)日：2017-03-21

申请号：US14970983

申请日：2015-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min Ryu ,  Ho-Young Song ,  Yun-Young Lee

IPC: G11C29/40 ,  G11C29/04 ,  G11C29/00 ,  G11C17/16 ,  G11C17/14 ,  G11C17/18 ,  G11C8/10 ,  G06F11/00 ,  G11C17/00

CPC classification number: G11C29/40 ,  G06F11/006 ,  G11C8/10 ,  G11C17/00 ,  G11C17/143 ,  G11C17/16 ,  G11C17/18 ,  G11C29/04 ,  G11C29/76

Abstract: Provided is a semiconductor device and a manufacturing method thereof. The semiconductor device may include a first cell array, a first fuse circuit, a first spare cell array, a second spare cell array, and a redundancy select controller. The first fuse circuit may be configured to store a first failed address corresponding to one or more defective memory cells in the first cell array. Each of the first and second spare cell arrays may include a plurality of spare memory cells configured to replace first and second defective memory cells in the first cell array, respectively. For replacing the first and second defective memory cells, the redundancy select controller may be configured to selectively assign the first fuse circuit to either one or both of the first and second spare cell arrays.

公开(公告)号：US09123407B2

公开(公告)日：2015-09-01

申请号：US14073987

申请日：2013-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min Ryu ,  Sung-Min Seo ,  Ju-Seop Park

IPC: G11C7/22 ,  G11C7/10 ,  G11C29/02 ,  G11C7/20 ,  G11C7/08 ,  G11C29/44

CPC classification number: G11C7/20 ,  G11C7/1063 ,  G11C7/22 ,  G11C7/222 ,  G11C29/028 ,  G11C2029/4402

Abstract: A data read start decision device includes: a storing circuit configured to store code key data; a read check circuit configured to output a read start signal in response to code key data read from the storing circuit, and a controller configured to start reading environment setting data from the storing circuit in response to the read start signal. The read check circuit is configured to at least one of: receive the read start signal from the controller and transfer the read start signal to the controller in response to the read code key data; and generate the read start signal based on the read code key data and output the read start signal to the controller.

Abstract translation: 数据读取开始判定装置包括：存储电路，被配置为存储代码密钥数据; 读取检查电路，被配置为响应于从存储电路读取的代码密钥数据输出读取开始信号，以及控制器，被配置为响应于读取的开始信号从存储电路开始读取环境设置数据。 读取检查电路被配置为以下中的至少一个：从控制器接收读取开始信号并响应于读取代码密钥数据将读取的开始信号传送到控制器; 并根据读取的代码键数据生成读取开始信号，并将读出的开始信号输出到控制器。