公开(公告)号：US09614002B1

公开(公告)日：2017-04-04

申请号：US15238720

申请日：2016-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Titash Rakshit ,  Borna J. Obradovic ,  Jorge Kittl ,  Joon Goo Hong

IPC: G11C11/16 ,  H01L27/22

CPC classification number: G11C11/16 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/224 ,  H01L43/08 ,  H01L43/12

Abstract: A bidirectional memory cell includes a write unit and a read unit. The write unit and the read unit each include an MTJ structure having a first and second pinned layers and a free layer. The first and second pinned layers are separated from the free layer by at least one tunnel barrier. The first pinned layer is electrically coupled to a first write line through a first diode. The second pinned layer is electrically connected to a second word line through a second diode. The free layer is electrically coupled to a first bit line. Additionally, the free layer of the read unit is magnetically coupled to the free layer of the write unit.

公开(公告)号：US12080703B2

公开(公告)日：2024-09-03

申请号：US18048186

申请日：2022-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vassilios Gerousis ,  Rwik Sengupta ,  Joon Goo Hong ,  Kevin Traynor ,  Tanya Abaya ,  Dharmendar Palle ,  Mark S. Rodder

IPC: H01L27/02 ,  G06F30/392 ,  H01L23/528

CPC classification number: H01L27/0207 ,  G06F30/392 ,  H01L23/5286

Abstract: A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.

公开(公告)号：US11475933B2

公开(公告)日：2022-10-18

申请号：US16847741

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan Hatcher ,  Titash Rakshit ,  Jorge Kittl ,  Joon Goo Hong ,  Dharmendar Palle

IPC: G11C11/16 ,  G06F17/16 ,  G06F17/17 ,  G06G7/16

Abstract: A method, system and electronic device for mitigating variance in a two transistor two resistive memory element (2T2R) circuit is provided. The method includes calculating a sum of a number of logical 1's in a column of bitcells in the 2T2R circuit, N, of an input vector, sensing output current values from each current line in the column of bitcells and calculating an inner product, M, of the input vector and the bitcells in the column in the 2T2R circuit based on the sensed output current values.

公开(公告)号：US11211493B2

公开(公告)日：2021-12-28

申请号：US16577815

申请日：2019-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Mark Rodder

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/66 ,  H01L29/66

Abstract: Apparatus and method are provided. The apparatus includes at least one field effect transistor (FET), wherein the at least one FET comprises at least one gate overlaying at least one non-linear fin, wherein the non-linear fin is formed via modulating a mandrel by producing cut-outs in the mandrel via optical proximity correction (OPC). The method includes receiving a semiconductor wafer, forming source and drain areas for each of at least one FET on the semiconductor wafer; and forming at least one gate overlaying at least one non-linear fin in each of the at least one FET, wherein the non-linear fin is formed via modulating a mandrel by producing cut-outs in the mandrel via OPC.

公开(公告)号：US10832774B2

公开(公告)日：2020-11-10

申请号：US16448820

申请日：2019-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Titash Rakshit ,  Jorge Kittl ,  Rwik Sengupta ,  Dharmendar Palle ,  Joon Goo Hong

IPC: G11C13/00 ,  G11C11/22 ,  G11C11/16

Abstract: A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, and a third FET, and a load resistor connected to a drain of the third FET.

公开(公告)号：US10811415B2

公开(公告)日：2020-10-20

申请号：US16298887

申请日：2019-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Joon Goo Hong ,  Vassilios Gerousis ,  Mark S. Rodder

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78

Abstract: According to some example embodiments of the present disclosure, a semiconductor device includes: a substrate; a first semiconductor layer over the substrate, the first semiconductor layer being a first type of semiconductor device; and a second semiconductor layer over the substrate and the first semiconductor layer, the second semiconductor layer being the first type of semiconductor device, wherein a first portion of the first semiconductor layer overlaps the second semiconductor layer when viewed in a direction perpendicular to a plane of the substrate and a second portion of the first semiconductor layer is laterally offset from the second semiconductor layer when viewed in the direction perpendicular to the plane of the substrate.

公开(公告)号：US10727297B2

公开(公告)日：2020-07-28

申请号：US15348916

申请日：2016-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Joon Goo Hong

IPC: H01L27/092 ,  H01L29/04 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/78

Abstract: A complimentary metal-oxide-semiconductor (CMOS) circuit including: a substrate; and a plurality of field-effect transistors on the substrate. Each of the field-effect transistors includes: a plurality of contacts; a source connected to one of the contacts; a drain connected to another one of the contacts; a gate; and a spacer between the gate and the contacts. The spacer of one of the field-effect transistors has a larger airgap than the spacer of another one of the field-effect transistors.

公开(公告)号：US20200152801A1

公开(公告)日：2020-05-14

申请号：US16390859

申请日：2019-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Mark Stephen Rodder ,  Joon Goo Hong ,  Titash Rakshit

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes first and second GAA FETs spaced apart by an inter-channel spacing. Each of the GAA FETs includes a horizontal nanosheet conductive channel structure, a gate material completely surrounding the horizontal nanosheet conductive channel structure, source and drain regions at opposite ends of the horizontal nanosheet conductive channel structure, source and drain contacts on the source and drain regions. A width of the horizontal nanosheet conductive channel structure of the first GAA FET or the second GAA FET is smaller than a maximum allowed width. The semiconductor device also includes a gate contact on the gate material in the inter-channel spacing between the first and second GAA FETs. The gate contact is spaced apart by a distance from each of the source and drain regions of the first and second GAA FETs in a range from a minimum design rule spacing to a maximum distance.

公开(公告)号：US20200066762A1

公开(公告)日：2020-02-27

申请号：US16666306

申请日：2019-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Kang Ill Seo ,  Borna J. Obradovic

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/477 ,  H01L27/088 ,  H01L21/027 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

Abstract: A method for providing a semiconductor device is described. The method provides a plurality of fins. A first portion of each of the plurality of fins is covered by a mask. A second portion of each of the plurality of fins is exposed by the mask. The method also performs an anneal in a volume-increasing ambient, such as hydrogen, at anneal temperature(s) above one hundred degrees Celsius and not more than six hundred degrees Celsius. The second portion of each of the fins is exposed during the anneal such that the second portion of each of the fins undergoes a volume expansion.

公开(公告)号：US20190148312A1

公开(公告)日：2019-05-16

申请号：US15927239

申请日：2018-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Harsono S. Simka ,  Ganesh Hegde ,  Joon Goo Hong ,  Rwik Sengupta ,  Mark S. Rodder

IPC: H01L23/00 ,  H01L23/522 ,  H01L27/02 ,  H04L9/32

CPC classification number: H01L23/573 ,  G09C1/00 ,  H01L23/5228 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L27/0207 ,  H04L9/3278

Abstract: A hardware-embedded security system is described. The system includes connective components, circuit elements and an insulator. The connective components include a variable conductivity layer that is conductive for a first stoichiometry and insulating for a second stoichiometry. The variable conductivity layer is conductive for a first portion of the connective components connected to a first portion of the circuit elements. The variable conductivity layer is insulating for a second portion of the connective components connected to a second portion of the circuit elements. Thus, the first portion of the circuit elements are active and the second portion of the circuit elements are inactive. The insulator is adjacent to at least a portion of each of the connective components. The first stoichiometry may be indistinguishable from the second stoichiometry via optical imaging and electron imaging of a portion of the insulator and the variable conductivity layer.