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    Controllers that generate output bits for storage in non-volatile memory devices by puncturing code word bits and methods for operating the same
    14.
    发明授权
    Controllers that generate output bits for storage in non-volatile memory devices by puncturing code word bits and methods for operating the same 有权
    通过对代码字位进行删截而产生用于存储在非易失性存储器件中的输出位的控制器和用于操作它们的方法

    公开(公告)号：US09239778B2

    公开(公告)日：2016-01-19

    申请号：US14054964

    申请日：2013-10-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kijun Lee ,  Junjin Kong ,  Dong-Min Shin ,  Kyeongcheol Yang ,  Seung-Chan Lim

    IPC: G06F3/00 ,  G06F13/00 ,  G06F12/00 ,  H03M13/11 ,  H03M13/13 ,  H03M13/00

    CPC classification number: G06F12/00 ,  H03M13/1111 ,  H03M13/1191 ,  H03M13/13 ,  H03M13/6362 ,  H04L1/0009

    Abstract: An operating method of a controller includes selecting bits of code word to be punctured; detecting locations of incapable bits of an input word based on locations of the bits to be punctured and a structure of a generation matrix calculation unit; refreezing the input word such that frozen bits and incapable bits of the input word overlap; generating input word bits by replacing information word bits with frozen bits based on the refreezing result; generating the code word by performing generation matrix calculation on the input word bits; generating output bits by puncturing the code word based on locations of the bits to be punctured; and transmitting the output bits to a nonvolatile memory device.

    Abstract translation: 控制器的操作方法包括选择要被穿孔的代码字的位; 基于要被删截的位的位置检测输入字的不能位的位置和生成矩阵计算单元的结构; 重新冻结输入字，使得输入字的冻结位和无效位重叠; 通过基于重新冻结结果将具有冻结位的信息字位替换来产生输入字位; 通过对输入字位执行生成矩阵计算来生成码字; 通过基于要被穿孔的比特的位置来对码字进行删截来产生输出比特; 并将输出比特发送到非易失性存储器件。

    Nonvolatile memory device and related data management method
    16.
    发明授权
    Nonvolatile memory device and related data management method 有权
    非易失性存储器件及相关数据管理方法

    公开(公告)号：US09335955B2

    公开(公告)日：2016-05-10

    申请号：US13935593

    申请日：2013-07-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kwanghoon Kim ,  Junjin Kong ,  Hong Rak Son

    IPC: G06F3/06 ,  G06F11/10

    CPC classification number: G06F3/0689 ,  G06F3/0619 ,  G06F3/0665 ,  G06F11/108

    Abstract: A method of operating a nonvolatile memory device comprising a plurality of memory blocks comprises storing first data and second data to be stored in a hot memory block of the memory blocks in a first buffer, transferring the first data stored in the first buffer to a second buffer to program the first data in the hot memory block, and generating RAID parity data based on the first and second data, wherein the RAID parity data and the first data form part of the same write stripe.

    Abstract translation: 一种操作包括多个存储器块的非易失性存储器件的方法包括将第一数据和第二数据存储在存储器块的热存储块中的第一缓冲器中，将存储在第一缓冲器中的第一数据传送到第二缓冲器 缓冲器，用于对所述热存储器块中的第一数据进行编程，以及基于所述第一和第二数据生成RAID奇偶校验数据，其中所述RAID奇偶校验数据和所述第一数据形成相同写入条带的一部分。

    ERROR CORRECTION DECODER AND OPERATION METHOD OF THE ERROR CORRECTION DECODER
    17.
    发明申请
    ERROR CORRECTION DECODER AND OPERATION METHOD OF THE ERROR CORRECTION DECODER 有权
    错误校正解码器的错误校正解码器和错误校正解码器的操作方法

    公开(公告)号：US20160103735A1

    公开(公告)日：2016-04-14

    申请号：US14877448

    申请日：2015-10-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kijun LEE ,  Myungkyu Lee ,  Sejin Lim ,  Junjin Kong

    IPC: G06F11/10 ,  H03M13/15

    CPC classification number: H03M13/3715 ,  H03M13/1525 ,  H03M13/1545 ,  H03M13/157

    Abstract: The inventive concepts relate to an operation method of an error correction decoder correcting an error of data read from a nonvolatile memory. The operation method may include receiving the data from the nonvolatile memory, performing a first error correction with respect to the received data in a simplified mode, and performing, when the first error correction fails in the simplified mode, a second error correction with respect to the received data in a full mode. When the first error correction of the simplified mode is performed, a part of operations of the second error correction of the full mode may be omitted.

    Abstract translation: 本发明构思涉及纠错解码器校正从非易失性存储器读取的数据的错误的操作方法。 操作方法可以包括从非易失性存储器接收数据，以简化模式对接收到的数据执行第一纠错，并且当在简化模式中第一错误校正失败时执行相对于 接收到的数据处于完整模式。 当执行简化模式的第一纠错时，可以省略完整模式的第二纠错的一部分操作。

    Methods of Performing Error Detection/Correction in Nonvolatile Memory Devices
    18.
    发明申请
    Methods of Performing Error Detection/Correction in Nonvolatile Memory Devices 有权
    在非易失性存储器件中执行错误检测/校正的方法

    公开(公告)号：US20140082458A1

    公开(公告)日：2014-03-20

    申请号：US14089361

    申请日：2013-11-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yong June Kim ,  Junjin Kong ,  KyoungLae Cho

    IPC: G06F11/10

    CPC classification number: G06F11/1072 ,  G06F11/1048 ,  G11C11/5642 ,  G11C16/3404 ,  G11C16/349

    Abstract: Methods of operating nonvolatile memory devices include testing strings of nonvolatile memory cells in the memory device to identify at least one weak string therein having a higher probability of yielding erroneous read data error relative to other strings. An identity of the at least one weak string may be stored as weak column information, which may be used to facilitate error detection and correction operations. In particular, an error correction operation may be performed on bits of data read from the strings using an algorithm that modifies a weighting of the reliability of one or more data bits in the bits of data based on the weak column information. More specifically, an algorithm may be used that interprets a bit of data read from the at least one weak string as having a relatively reduced reliability relative to other ones of the data bits.

    Abstract translation: 操作非易失性存储器件的方法包括测试存储器件中的非易失性存储器单元的串，以识别其中至少一个弱串，其中相对于其它串产生错误的读数据误差的概率较高。 至少一个弱字符串的身份可以存储为弱列信息，其可以用于促进错误检测和校正操作。 特别地，可以使用基于弱列信息修改数据位中的一个或多个数据位的可靠性的加权的算法来对从字符串读取的数据的位进行纠错操作。 更具体地，可以使用解释从至少一个弱串读取的数据位相对于其他数据位相对降低的可靠性的算法。

    Memory device performing refresh operation and method of operating the same
    20.
    发明授权
    Memory device performing refresh operation and method of operating the same 有权

    公开(公告)号：US11631448B1

    公开(公告)日：2023-04-18

    申请号：US17244466

    申请日：2021-04-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eunae Lee ,  Sunghye Cho ,  Kijun Lee ,  Junjin Kong ,  Yeonggeol Song

    IPC: G11C11/406 ,  G06F12/06

    Abstract: A memory device includes a memory cell array, an address manager and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The address manager samples access addresses provided from a memory controller to generate sampling addresses and determines a capture address from among the access addresses, based on a time interval between refresh commands from the memory controller. The refresh controller refreshes target memory cells from among the plurality of memory cells based on one of a maximum access address from among the sampling address and the captured address.

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