公开(公告)号：US11152074B2

公开(公告)日：2021-10-19

申请号：US16998273

申请日：2020-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Joe ,  Kang-Bin Lee

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/28 ,  H01L23/00 ,  G11C16/24 ,  G11C16/04 ,  G11C7/10 ,  G11C16/08

Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and connected to the memory cell region by the first and second metal pads, and a memory cell array in the memory cell region and including cell strings. The cell strings include memory cells, word lines and dummy lines connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings. The memory device further includes control logic in the peripheral circuit region and including a precharge control circuit that controls a precharge on partial cell strings among the cell strings and controls data program steps on the memory cells, and a row decoder in the peripheral circuit region that activates at least some of the word lines based on control of the control logic.

公开(公告)号：US20210065806A1

公开(公告)日：2021-03-04

申请号：US16935535

申请日：2020-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Jae-Duk Yu ,  Kang-Bin Lee ,  Sang-Won Shim ,  Bongsoon Lim

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

公开(公告)号：US20200381065A1

公开(公告)日：2020-12-03

申请号：US16998273

申请日：2020-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-MIN JOE ,  Kang-Bin Lee

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/28 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  G11C7/10 ,  H01L23/00

Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and connected to the memory cell region by the first and second metal pads, and a memory cell array in the memory cell region and including cell strings. The cell strings include memory cells, word lines and dummy lines connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings. The memory device further includes control logic in the peripheral circuit region and including a precharge control circuit that controls a precharge on partial cell strings among the cell strings and controls data program steps on the memory cells, and a row decoder in the peripheral circuit region that activates at least some of the word lines based on control of the control logic.

公开(公告)号：US11217311B2

公开(公告)日：2022-01-04

申请号：US16927100

申请日：2020-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Joe ,  Kang-Bin Lee

IPC: G11C16/08 ,  G11C16/10 ,  G11C16/04 ,  G11C16/24 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.

公开(公告)号：US11043274B2

公开(公告)日：2021-06-22

申请号：US16851622

申请日：2020-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Jae-Duk Yu ,  Kang-Bin Lee ,  Sang-Won Shim ,  Bongsoon Lim

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/04 ,  G11C7/10 ,  G11C7/22 ,  G11C16/26

Abstract: Each of memory blocks of a nonvolatile memory device includes first memory cells of a first portion of pillar and second memory cells of a second portion of the pillar. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary.

公开(公告)号：US10854250B2

公开(公告)日：2020-12-01

申请号：US15997964

申请日：2018-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Yun Lee ,  Joon Soo Kwon ,  Byung Soo Kim ,  Su-Yong Kim ,  Sang-Soo Park ,  Il Han Park ,  Kang-Bin Lee ,  Jong-Hoon Lee ,  Na-Young Choi

IPC: G11C8/08 ,  G11C29/12 ,  G11C16/30 ,  G11C16/08 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G06F3/06 ,  G11C5/14 ,  G11C16/12 ,  G11C16/14 ,  G11C29/02

Abstract: A memory device comprises a memory cell array including a first memory cell disposed on a substrate and a second memory cell above the first memory cell; a first word line connected to the first memory cell and a second word line connected to the second memory cell, the second word line disposed above the first word line; and a word line defect detection circuit configured to monitor a number of pulses of a pumping clock signal while applying a first voltage to the first word line to detect a defect of the first word line. The voltage generator is configured to apply a second voltage different from the first voltage to the second word line for programming the second memory cell when the number of pulses of the pumping clock signal is smaller than a reference value.

公开(公告)号：US20190318784A1

公开(公告)日：2019-10-17

申请号：US16213420

申请日：2018-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang-Bin Lee ,  Il-Han Park ,  Jong-Hoo Jo

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

Abstract: In a method of programming in a nonvolatile memory device, channels of a plurality of cell strings are precharged through ground selection transistors by a precharge voltage of a source line. A turn-on voltage is applied to a selected ground selection transistor of a selected cell string among the plurality of cell strings, during a verification read period of an N-th program loop. The turn-on voltage applied to the selected ground selection transistor is maintained to precharge the channels for an (N+1)-th program loop, without recovery after the verification read period of the N-th program loop is finished. Power consumption is reduced and an operation speed is increased by maintaining the turn-on voltage of the selected ground selection line to precharge the channels of the cell strings without recovery after the verification read operation is finished.

公开(公告)号：US09564229B2

公开(公告)日：2017-02-07

申请号：US15229158

申请日：2016-08-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon-Hee Choi ,  Sang-Wan Nam ,  Kang-Bin Lee

IPC: G11C11/34 ,  G11C16/10 ,  G11C16/04 ,  G11C11/56 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C7/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/30 ,  G11C16/3459

Abstract: In a method of programming a three-dimensional nonvolatile memory device, a program loop is executed at least one time, wherein the program loop includes a programming step for programming selected memory cells among the memory cells and a verifying step for verifying whether the selected memory cells are program-passed or not. In the programming the selected memory cells, a level of a voltage being applied to a common source line connected to the strings in common may be changed. Thus, in a program operation, power consumption which is needed to charge-discharge the common source line can be decreased while increasing boosting efficiency.

Abstract translation: 在编程三维非易失性存储器件的方法中，程序循环至少执行一次，其中程序循环包括编程步骤，用于对存储器单元之间选择的存储单元进行编程，以及验证步骤，用于验证所选择的存储器 单元格是否通过程序传递。 在对所选存储单元的编程中，可以改变施加到共同连接到串的公共源极线的电压电平。 因此，在程序运行中，能够提高提升效率的同时，能够减小对公共源极线进行充放电所需要的功耗。

公开(公告)号：US12046287B2

公开(公告)日：2024-07-23

申请号：US18173730

申请日：2023-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Joe ,  Kang-Bin Lee

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  H01L24/05 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.