公开(公告)号：US09040415B2

公开(公告)日：2015-05-26

申请号：US14286108

申请日：2014-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Bo-Un Yoon ,  Young-Sang Youn ,  Jeong-Nam Han ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Byung-Kwon Cho ,  Ji-Hoon Cha

IPC: H01L21/4763 ,  H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66553 ,  H01L29/66795 ,  H01L2221/1063

Abstract: A method for forming a trench includes etching an oxide layer to form a trench therein, conformally forming a first reaction layer along a surface of the trench, the first reaction layer including a first region on an upper portion of the trench and a second region on a lower portion of the trench, forming a barrier layer by reacting a first amount of etching gas with the first region of the first reaction layer, and etching the oxide layer on a lower portion of the second region by reacting a second amount of etching gas with the second region of the first reaction layer, the second amount of etching gas being greater than the first amount of etching gas.

Abstract translation: 一种用于形成沟槽的方法包括蚀刻氧化物层以在其中形成沟槽，沿着沟槽的表面共形形成第一反应层，第一反应层包括沟槽上部的第一区域和第二区域 沟槽的下部，通过使第一量的蚀刻气体与第一反应层的第一区域反应形成阻挡层，并且通过使第二量的蚀刻气体反应来蚀刻第二区域的下部的氧化物层 与第一反应层的第二区域相比，第二量的蚀刻气体大于第一量的蚀刻气体。

公开(公告)号：US20150028423A1

公开(公告)日：2015-01-29

申请号：US14513807

申请日：2014-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine Park ,  Boun Yoon ,  Jeongnam Han ,  Kee-Sang Kwon ,  Byung-Kwon Cho ,  Wonsang Choi

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/161 ,  H01L29/45

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/161 ,  H01L29/4175 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.

Abstract translation: 使用双金属硅化物层制造半导体器件。 半导体器件包括具有第一和第二区域的衬底，第一区域中的衬底上的第一金属栅电极，第二区域中的衬底上的第二金属栅电极，两侧的衬底上的第一外延层 的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层， 在第一和第二金属硅化物层上的电介质层，通过层间电介质层并电连接到第一和第二金属硅化物层的接触插塞。

公开(公告)号：US20170345825A1

公开(公告)日：2017-11-30

申请号：US15680960

申请日：2017-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC: H01L27/11 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/762 ,  H01L27/092 ,  H01L27/088 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

公开(公告)号：US08889552B2

公开(公告)日：2014-11-18

申请号：US14083654

申请日：2013-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangline Park ,  Boun Yoon ,  Jeongnam Han ,  Kee-Sang Kwon ,  Byung-Kwon Cho ,  Wongsang Choi

IPC: H01L21/44 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/161 ,  H01L29/4175 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.

Abstract translation: 使用双金属硅化物层制造半导体器件。 半导体器件包括具有第一和第二区域的衬底，第一区域中的衬底上的第一金属栅电极，第二区域中的衬底上的第二金属栅电极，两侧的衬底上的第一外延层 的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层， 在第一和第二金属硅化物层上的电介质层，通过层间电介质层并电连接到第一和第二金属硅化物层的接触插塞。

公开(公告)号：US08841769B2

公开(公告)日：2014-09-23

申请号：US13796195

申请日：2013-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine Park ,  Boun Yoon ,  Jeongnam Han ,  Kee-Sang Kwon ,  Wonsang Choi

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/44 ,  H01L21/4763 ,  H01L23/485 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first insulating layer on a substrate; a first contact hole passing through the first insulating layer and exposing an upper surface of the substrate; a first barrier metal layer disposed on a sidewall and at a bottom of the first contact hole and a first metal plug disposed on the first barrier metal layer and in the first contact hole. A recess region is between the first insulating layer and the first metal plug. A gap-fill layer fills the recess region; and a second insulating layer is on the gap-fill layer. A second contact hole passes through the second insulating layer and exposes the upper surface of the first metal plug. A second barrier metal layer is on a sidewall and at the bottom of the second contact hole; and a second metal plug is on the second barrier metal layer.

Abstract translation: 半导体器件包括：衬底上的第一绝缘层; 穿过所述第一绝缘层并暴露所述衬底的上表面的第一接触孔; 设置在第一接触孔的侧壁和底部的第一阻挡金属层和设置在第一阻挡金属层上和第一接触孔中的第一金属栓。 凹部区域位于第一绝缘层和第一金属插塞之间。 间隙填充层填充凹部区域; 并且间隙填充层上的第二绝缘层。 第二接触孔穿过第二绝缘层并暴露第一金属插塞的上表面。 第二阻挡金属层位于第二接触孔的侧壁和底部; 并且第二金属塞在第二阻挡金属层上。

公开(公告)号：US20140048939A1

公开(公告)日：2014-02-20

申请号：US13796195

申请日：2013-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjine Park ,  Boun Yoon ,  Jeongnam Han ,  Kee-Sang Kwon ,  Wonsang Choi

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first insulating layer on a substrate; a first contact hole passing through the first insulating layer and exposing an upper surface of the substrate; a first barrier metal layer disposed on a sidewall and at a bottom of the first contact hole and a first metal plug disposed on the first barrier metal layer and in the first contact hole. A recess region is between the first insulating layer and the first metal plug. A gap-fill layer fills the recess region; and a second insulating layer is on the gap-fill layer. A second contact hole passes through the second insulating layer and exposes the upper surface of the first metal plug. A second barrier metal layer is on a sidewall and at the bottom of the second contact hole; and a second metal plug is on the second barrier metal layer.

Abstract translation: 半导体器件包括：衬底上的第一绝缘层; 穿过所述第一绝缘层并暴露所述衬底的上表面的第一接触孔; 设置在第一接触孔的侧壁和底部的第一阻挡金属层和设置在第一阻挡金属层上和第一接触孔中的第一金属栓。 凹部区域位于第一绝缘层和第一金属插塞之间。 间隙填充层填充凹部区域; 并且间隙填充层上的第二绝缘层。 第二接触孔穿过第二绝缘层并暴露第一金属插塞的上表面。 第二阻挡金属层位于第二接触孔的侧壁和底部; 并且第二金属塞在第二阻挡金属层上。