公开(公告)号：US20250098264A1

公开(公告)日：2025-03-20

申请号：US18604031

申请日：2024-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangcheol NA ,  Beomjin KIM ,  Yoolim AHN ,  Kyoungwoo LEE ,  Minseung LEE ,  Hyeryeong LEE ,  Keun Hwi CHO ,  Seungseok HA

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes an insulating layer including a first surface, a second surface, and an element isolation trench, an insulating pattern on the first surface of the insulating layer, an active pattern on the insulating pattern and including channel patterns, a source/drain pattern on at least one side of the active pattern, a lower wiring structure on the second surface of the insulating layer, and a through-via that extending in the insulating layer and connecting the source/drain pattern and the lower wiring structure, where the insulating pattern may include a first portion between the insulating layer and the active pattern, a second portion surrounding at least a portion of the through-via, and a third portion on a bottom surface of the element isolation trench.

公开(公告)号：US20240014288A1

公开(公告)日：2024-01-11

申请号：US18369450

申请日：2023-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guk Il AN ,  Keun Hwi CHO ,  Dae Won HA ,  Seung Seok HA

IPC: H01L23/522 ,  H01L27/088 ,  H01L23/528 ,  H01L29/417

CPC classification number: H01L23/5223 ,  H01L27/0886 ,  H01L23/5283 ,  H01L29/41791

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.

公开(公告)号：US20220190136A1

公开(公告)日：2022-06-16

申请号：US17686504

申请日：2022-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungseok HA ,  Gukil AN ,  Keun Hwi CHO ,  Sungmin KIM

IPC: H01L29/51 ,  H01L29/49 ,  H01L29/786 ,  H01L29/423

Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a substrate, a pair of semiconductor patterns adjacent to each other on the substrate, a gate electrode on the pair of semiconductor patterns, a source/drain pattern connected to the pair of semiconductor patterns, and a ferroelectric pattern on surfaces of the pair of semiconductor patterns. The surfaces of the pair of semiconductor patterns may face each other, and the ferroelectric pattern may define a first space between the pair of semiconductor patterns. The gate electrode may include a work function metal pattern that is in the first space.

公开(公告)号：US20200043928A1

公开(公告)日：2020-02-06

申请号：US16354369

申请日：2019-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo Jin KIM ,  Dae Won HA ,  Yoon Moon PARK ,  Keun Hwi CHO

IPC: H01L27/092

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first transistor including a single first active fin disposed in the first region, a first gate electrode intersecting the single first active fin, and a single first source/drain layer disposed in the first recess of the single first active fin, and a second transistor including a plurality of second active fins disposed in the second region, a second gate electrode intersecting the plurality of second active fins, and a plurality of second source/drain layers disposed in the second recesses of the plurality of second active fins. The single first active fin and the plurality of second active fins may have a first conductivity type, and a depth of the first recess may be less than a depth of each of the second recesses.

公开(公告)号：US20200013871A1

公开(公告)日：2020-01-09

申请号：US16425337

申请日：2019-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guk Il AN ,  Keun Hwi CHO ,  Dae Won HA ,  Seung Seok HA

IPC: H01L29/51 ,  H01L23/522 ,  H01L49/02 ,  H01L29/78 ,  H01L27/088

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.

公开(公告)号：US20240136356A1

公开(公告)日：2024-04-25

申请号：US18379731

申请日：2023-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byeol Hae EOM ,  Byung Ha CHOI ,  Keun Hwi CHO ,  Sung Won KIM ,  Yuri MASUOKA ,  Won Cheol JEONG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device includes a first element separation structure, a second element separation structure, and a third element separation structure sequentially disposed along a first direction and extending in a second direction intersecting the first direction; a first active pattern extending in the first direction between the first element separation structure and the second element separation structure; a second active pattern extending in the first direction between the second element separation structure and the third element separation structure and separated from the first active pattern by the second element separation structure; a first gate electrode extending in the second direction on the first active pattern; and a plurality of second gate electrodes extending in the second direction on the second active pattern, wherein a width of the first active pattern in the second direction is greater than a width of the second active pattern in the second direction.

公开(公告)号：US20230299139A1

公开(公告)日：2023-09-21

申请号：US18057986

申请日：2022-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hwi CHO ,  Myung Gil KANG ,  Gibum KIM ,  Dongwon KIM

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/66439

Abstract: A semiconductor device includes an active region on a substrate, source/drain patterns on the active region, channel patterns on the active region and connected to the source/drain patterns, each of the channel patterns including a plurality of semiconductor patterns, which are vertically stacked to be spaced apart from each other, gate electrodes, which are respectively on the channel patterns and are extended in a first direction and parallel to each other, and active contacts, which are electrically and respectively connected to the source/drain patterns. A bottom surface of a first active contact is located at a first level, and a bottom surface of a second active contact is located at a second level higher than the first level. A bottom surface of a third active contact is located at a third level higher than the second level.

公开(公告)号：US20230170386A1

公开(公告)日：2023-06-01

申请号：US17888639

申请日：2022-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho Jin LEE ,  Beom Jin PARK ,  Myoung Sun LEE ,  Keun Hwi CHO ,  Dong Won KIM

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L29/775 ,  H01L29/6656 ,  H01L29/78696

Abstract: A semiconductor device includes first to fourth active patterns extending in a horizontal first direction. The second active pattern is spaced apart from the first active pattern in the first direction. The third active pattern is spaced apart from the first active pattern in a horizontal second direction. The fourth active pattern is spaced apart from the third active pattern in the first direction. A field insulating layer surrounds a sidewall of each of the first to fourth active patterns. First to fourth pluralities of nanosheets are respectively disposed the first to fourth active patterns. A first gate electrode extends in the second direction, intersects each of the first and third active patterns, and surrounds the first and third pluralities of nanosheets. A second gate electrode extends in the second direction, intersects each of the second and fourth active patterns, and surrounds the second and fourth pluralities of nanosheets.

公开(公告)号：US20220384623A1

公开(公告)日：2022-12-01

申请号：US17886612

申请日：2022-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil KANG ,  Dongwon KIM ,  Minyi KIM ,  Keun Hwi CHO

IPC: H01L29/732 ,  H01L21/8228 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/735

Abstract: A semiconductor device including a well region in a substrate, an impurity region in the well region, a first active fin on the impurity region, a second active fin on the well region, and a connection pattern penetrating the second active fin and connected to the well region may be provided. The substrate and the impurity region include impurities having a first conductivity type. The well region includes impurities having a second conductivity type different from the first conductivity type. The first active fin includes a plurality of first semiconductor patterns that are spaced apart from each other in a direction perpendicular to a top surface of the substrate. The first semiconductor patterns and the impurity region include impurities having the first conductivity type.

公开(公告)号：US20220157853A1

公开(公告)日：2022-05-19

申请号：US17369236

申请日：2021-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hwi CHO ,  Sangdeok KWON ,  Dae Sin KIM ,  Dongwon KIM ,  Yonghee PARK ,  Hagju CHO

IPC: H01L27/118 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8238

Abstract: A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.