公开(公告)号：US11557332B2

公开(公告)日：2023-01-17

申请号：US17322227

申请日：2021-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn Cha ,  Hyun-Gi Kim ,  Hoon Sin ,  Ye-Sin Ryu ,  In-Woo Jun

IPC: G11C7/00 ,  G11C11/406 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

公开(公告)号：US11385960B2

公开(公告)日：2022-07-12

申请号：US16894354

申请日：2020-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Uhn Cha

IPC: G06F11/10 ,  H03M13/15

Abstract: A semiconductor memory device is provided. The device includes a memory cell array including a plurality of dynamic memory cells; an error correction code (ECC) engine; an input/output (I/O) gating circuit connected between the ECC engine and the memory cell array; an error information register configured to store an error address and a first syndrome, the error address and the first syndrome being associated with a first error bit in a first codeword stored in a first page of the memory cell array; and a control logic configured to, based on the first codeword being read again and including a second error bit which is different from the first error bit, recover a second syndrome associated with the second error bit by using the first syndrome stored in the error information register and sequentially correct the first error bit and the second error bit.

公开(公告)号：US11194657B2

公开(公告)日：2021-12-07

申请号：US16823443

申请日：2020-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Uhn Cha ,  Kyung-Ryun Kim ,  Young-Hun Seo

IPC: G06F11/10 ,  G11C29/52 ,  G11C11/4093 ,  G11C11/4096 ,  H01L25/065 ,  G11C11/407 ,  G11C5/04

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a plurality of bank arrays, and each of the bank arrays includes dynamic memory cells. The control logic circuit generates a first control signal to control the I/O gating circuit and a second control signal to control the ECC engine, in response to an access address and a command. The control logic circuit controls the ECC engine to perform s-bit ECC encoding on a write data to be stored in a first page of at least one bank array, in response to a first command, and controls the ECC engine to perform t-bit ECC decoding on a first codeword read from the first page, in response to a second command.

公开(公告)号：US10255989B2

公开(公告)日：2019-04-09

申请号：US15233088

申请日：2016-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Uhn Cha ,  Hoi-Ju Chung

IPC: G06F11/10 ,  G11C29/52 ,  G11C11/406 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4076 ,  G11C29/00 ,  G11C11/16

Abstract: A semiconductor memory device includes a memory cell array and a main controller. The memory cell array includes a plurality of memory bank arrays, and each of the memory bank arrays includes a plurality of pages. The main controller counts a number of accesses to a first memory region of the memory cell array, generates at least one victim address of at least one neighbor memory region that is adjacent to the first memory region and performs a scrubbing operation sub-pages of the pages corresponding to the at least one victim address when the counted number of accesses reaches a first reference value during a reference interval.

公开(公告)号：US10198221B2

公开(公告)日：2019-02-05

申请号：US15969042

申请日：2018-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn Cha ,  Hoi-Ju Chung ,  Uk-Song Kang

IPC: G11C11/34 ,  G06F3/06 ,  G11C29/52 ,  G06F11/10 ,  G11C11/16

Abstract: A method of scrubbing errors from a semiconductor memory device including a memory cell array and an error correction circuit, can be provided by accessing a page of the memory cell array to provide a data that includes sub units that are separately writable to the page of memory and to provide parity data configured to detect and correct a bit error in the data and selectively enabling write-back of a selected sub unit of the data responsive to determining that the selected sub unit of data includes a correctable error upon access as part of an error scrubbing operation.

公开(公告)号：US10127102B2

公开(公告)日：2018-11-13

申请号：US15229774

申请日：2016-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ye-Sin Ryu ,  Hoi-Ju Chung ,  Sang-Uhn Cha ,  Young-Yong Byun ,  Seong-Jin Jang

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06

Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, an error correction circuit and a first path selection circuit. The memory cell array includes a plurality of bank arrays. The control logic circuit controls access to the memory cell array and generates a density mode signal based on a command. The first path selection circuit selectively provides write data to the error correction circuit.

公开(公告)号：US20180322008A1

公开(公告)日：2018-11-08

申请号：US16015534

申请日：2018-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoi-Ju Chung ,  Sang-Uhn Cha ,  Ho-Young Song ,  Hyun-Joong Kim

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C29/00 ,  G11C29/04

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G11C29/52 ,  G11C29/70 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

公开(公告)号：US10037244B2

公开(公告)日：2018-07-31

申请号：US15238216

申请日：2016-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoi-Ju Chung ,  Sang-Uhn Cha ,  Ho-Young Song ,  Hyun-Joong Kim

IPC: G11C7/00 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C29/00 ,  G11C29/04

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G11C29/52 ,  G11C29/70 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

公开(公告)号：US09805827B2

公开(公告)日：2017-10-31

申请号：US14817212

申请日：2015-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil Son ,  Chul-Woo Park ,  Hoi-Ju Chung ,  Sang-Uhn Cha ,  Seong-Jin Jang

IPC: G11C11/16 ,  G11C11/4096 ,  G11C29/42 ,  G11C29/44

CPC classification number: G11C29/4401 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/4096 ,  G11C29/42 ,  G11C2029/4402

Abstract: A semiconductor memory device includes a memory cell array and a test circuit. The test circuit reads data stream from the memory cell array, configured to, on comparing bits of each first unit in the data stream, compares corresponding bits in the first units as each second unit and outputs a fail information signal including pass/fail information on the data stream and additional information on the data stream, in a test mode of the semiconductor memory device.

公开(公告)号：US11593199B2

公开(公告)日：2023-02-28

申请号：US17562505

申请日：2021-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoi-Ju Chung ,  Sang-Uhn Cha ,  Ho-Young Song ,  Hyun-Joong Kim

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C29/00 ,  G11C29/04

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.