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    Integrated circuit devices including a vertical field-effect transistor (VFET) and methods of forming the same
    12.
    发明授权
    Integrated circuit devices including a vertical field-effect transistor (VFET) and methods of forming the same 有权

    公开(公告)号：US11107906B2

    公开(公告)日：2021-08-31

    申请号：US16798482

    申请日：2020-02-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chang Woo Sohn ,  Seung Hyun Song ,  Seon-Bae Kim ,  Min Cheol Oh ,  Young Chai Jung

    IPC: H01L29/66

    Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include forming a dummy channel region and an active region of a substrate, forming a bottom source/drain region on the active region, forming a gate electrode on one of opposing side surfaces of the dummy channel region, and forming first and second spacers on the opposing side surfaces of the dummy channel region, respectively. The gate electrode may include a first portion on the one of the opposing side surfaces of the dummy channel region and a second portion between the bottom source/drain region and the first spacer. The methods may also include forming a bottom source/drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source/drain contact may electrically connect the second portion of the gate electrode to the bottom source/drain region.

    Integrated circuit devices including a vertical field-effect transistor (VFET) and methods of forming the same
    16.
    发明授权
    Integrated circuit devices including a vertical field-effect transistor (VFET) and methods of forming the same 有权

    公开(公告)号：US11552182B2

    公开(公告)日：2023-01-10

    申请号：US17399118

    申请日：2021-08-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chang Woo Sohn ,  Seung Hyun Song ,  Seon-Bae Kim ,  Min Cheol Oh ,  Young Chai Jung

    IPC: H01L29/66

    Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include forming a dummy channel region and an active region of a substrate, forming a bottom source/drain region on the active region, forming a gate electrode on one of opposing side surfaces of the dummy channel region, and forming first and second spacers on the opposing side surfaces of the dummy channel region, respectively. The gate electrode may include a first portion on the one of the opposing side surfaces of the dummy channel region and a second portion between the bottom source/drain region and the first spacer. The methods may also include forming a bottom source/drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source/drain contact may electrically connect the second portion of the gate electrode to the bottom source/drain region.

    Integrated circuit devices including transistors having variable channel pitches
    17.
    发明授权
    Integrated circuit devices including transistors having variable channel pitches 有权

    公开(公告)号：US11043564B2

    公开(公告)日：2021-06-22

    申请号：US16520717

    申请日：2019-07-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Ho Do ,  Seung Hyun Song

    IPC: H01L29/417 ,  H01L27/02 ,  H01L29/78 ,  H01L27/088

    Abstract: Integrated circuit devices may include active regions spaced apart from each other in a direction. The active regions may include a first pair of active regions, a second pair of active regions, and a third pair of active regions. The first pair of active regions may be spaced apart from each other by a first distance in the direction, the second pair of active regions may be spaced apart from each other by the first distance in the direction, and the third pair of active regions may be spaced apart from each other by the first distance in the direction. The second pair of active regions may be spaced apart from the first pair of active regions and the third pair of active regions by a second distance in the direction, and the first distance may be shorter than the second distance.

    Semiconductor device
    19.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US09773785B2

    公开(公告)日：2017-09-26

    申请号：US15219374

    申请日：2016-07-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyu Baik Chang ,  Byoung Hak Hong ,  Yoon Suk Kim ,  Seung Hyun Song

    IPC: H01L27/088 ,  H01L29/06 ,  H01L27/092 ,  H01L29/78

    CPC classification number: H01L27/0886 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L27/0924 ,  H01L29/7843 ,  H01L29/7845

    Abstract: A semiconductor device includes first and second fins on first and second regions of a substrate, a first trench overlapping a vertical end portion of the first fin and including first upper and lower portions, the first upper and lower portions separated by an upper surface of the first fin, a second trench overlapping a vertical end portion of the second fin and including second upper and lower portions separated by an upper surface of the second fin, a first dummy gate electrode including first metal oxide and filling layers, the first metal oxide layer filling the first lower portion of the first trench and is along a sidewall of the first upper portion of the first trench, and a second dummy gate electrode filling the second trench and including second metal oxide and filling layers, the second metal oxide layer extending along sidewalls of the second trench.

    Fin structure for vertical field effect transistor having two-dimensional shape in plan view
    20.
    发明授权
    Fin structure for vertical field effect transistor having two-dimensional shape in plan view 有权

    公开(公告)号：US11271091B2

    公开(公告)日：2022-03-08

    申请号：US16775550

    申请日：2020-01-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seon Bae Kim ,  Seung Hyun Song ,  Ki Il Kim ,  Young Chai Jung

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L29/78

    Abstract: A method for manufacturing a fin structure for a vertical field effect transistor (VFET) includes: forming on a substrate mandrels having at least one first gap therebetween; forming first spacers on side surfaces of the mandrels such that at least one second gap, smaller than the first gap, is formed between the first spacers; forming a second spacer on side surfaces of the first spacers; removing the mandrels and the first spacers to leave the second spacer on the side surfaces of the first spacers; removing the second spacer, on the side surfaces of the first spacers, at a predetermined portion so that the remaining second spacer has a same two-dimensional (2D) shape as the fin structure; and removing a portion of the substrate, except below the remaining second spacer, and the remaining second spacer so that the substrate below the remaining second spacer forms the fin structure.

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