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公开(公告)号：US11238942B2
公开(公告)日：2022-02-01
申请号：US17023556
申请日：2020-09-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seung-Bum Kim , Il-Han Park , Ji-Young Lee , Su-Chang Jeon
Abstract: Nonvolatile memory device includes memory cell region including a first metal pad and a second metal pad, peripheral circuit region including a third metal pad and a fourth metal pad, vertically connected to the memory cell region. The nonvolatile memory device includes a page buffer circuit including page buffers to sense data from selected memory cells, each including two sequential sensing operations to determine one data state, and each of the page buffers including a latch to sequentially store results of the two sequential sensing operations. The nonvolatile memory device includes control circuit in the peripheral circuit region, to control the page buffers to store result of the first read operation, reset the latches after completion of the first read operation, and control the page buffers to perform the second read operation based on a valley determined based on the result of the first read operation.
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公开(公告)号：US10937508B2
公开(公告)日：2021-03-02
申请号：US16364588
申请日：2019-03-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seung-Bum Kim , Il-Han Park , Ji-Young Lee , Su-Chang Jeon
IPC: G11C16/26 , G11C11/56 , G11C16/24 , G11C16/10 , G11C16/34 , G06F11/10 , G11C29/52 , G11C16/14 , G11C16/04
Abstract: Nonvolatile memory device includes a memory cell array including pages, each of the pages including memory cells storing data bits, each of the data bits being selectable by a different threshold voltage, a page buffer circuit coupled to the memory cell array through bit-lines, the page buffer circuit including page buffers to sense data from selected memory cells, and perform a first read operation and a second read operation, each including two sequential sensing operations to determine one data state, and each of the page buffers including a latch configured to sequentially store results of the two sequential sensing operations, and a control circuit to control the page buffers to store a result of the first read operation, reset the latches after completion of the first read operation, and perform the second read operation based on a valley determined based on the result of the first read operation.
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公开(公告)号：US10680005B2
公开(公告)日：2020-06-09
申请号：US16108302
申请日：2018-08-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seung-Bum Kim , Chan-Ho Kim
IPC: G11C29/00 , H01L27/11551 , H01L27/11578 , G11C5/02 , G11C29/42 , G11C16/34 , G11C29/52 , G11C16/10 , G11C11/56 , H01L27/11582 , H01L27/1157 , G11C29/04
Abstract: A nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory blocks, each including a plurality memory cells coupled to word-lines respectively, and the word-lines are stacked vertically on a substrate. The control circuit divides a first memory block of the plurality of memory blocks into a partial bad region and a partial normal region based on error information of an uncorrectable error of the first memory block which is designated as a bad block. The control circuit performs a memory operation on the partial normal region by applying a first bias condition to the partial bad region and by applying a second bias condition to the partial normal region, based on a command and an address, and the first bias condition is different from the second bias condition.
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公开(公告)号：US09019773B2
公开(公告)日：2015-04-28
申请号：US14037582
申请日：2013-09-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Il Han Park , Seung-Bum Kim
CPC classification number: G11C16/3445 , G11C11/5635 , G11C16/0483 , G11C16/3436 , G11C16/344
Abstract: A nonvolatile memory device includes a memory cell array and control logic. The memory cell array includes multiple memory blocks, each memory block including memory cells connected to word lines and bit lines. The control logic is configured to perform an erase operation in which an erase voltage is applied to a memory block of the multiple memory blocks to erase the memory cells of the memory block, and in which an erase verification voltage is applied a selected word line of the memory block to verify respective erase states of memory cells connected to the selected word line. The control logic is further configured to apply a read voltage to the selected word line to extract erase state information of the memory cells, and to control a level of the erase verification voltage based on the erase state information.
Abstract translation: 非易失性存储器件包括存储单元阵列和控制逻辑。 存储单元阵列包括多个存储块，每个存储块包括连接到字线和位线的存储器单元。 控制逻辑被配置为执行擦除操作，其中擦除电压被施加到多个存储块的存储块以擦除存储块的存储单元，并且其中擦除验证电压被施加到所选择的字线 所述存储块用于验证连接到所选字线的存储单元的相应擦除状态。 控制逻辑还被配置为向所选字线施加读取电压以提取存储器单元的擦除状态信息，并且基于擦除状态信息来控制擦除验证电压的电平。
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公开(公告)号：US11334250B2
公开(公告)日：2022-05-17
申请号：US16892512
申请日：2020-06-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seung-Bum Kim
IPC: G06F3/06 , G11C16/30 , G11C5/14 , H01L27/1157 , H01L27/11565 , G06F11/10 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26 , G11C29/52 , G11C29/04 , G11C29/12 , H01L27/11582
Abstract: Nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory blocks, the memory blocks including a plurality of memory cells coupled to word-lines respectively, the word-lines are stacked vertically on a substrate, and some memory cells of the plurality of memory cells are selected by sub-block unit smaller than one memory block. The control circuit divides sub-blocks of a first memory block into at least one bad sub-block and at least one normal sub-block based on error occurrence frequency of each of the sub-blocks, and applies different program/erase cycles to the at least one bad sub-block and the at least one normal sub-block based on a command and an address provided from external to the nonvolatile memory device. The at least one bad sub-block and the at least one normal sub-block are adjacent each other.
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Patent Agency Ranking
公开(公告)号：US11315646B2
公开(公告)日：2022-04-26
申请号：US17141408
申请日：2021-01-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seung-Bum Kim , Min-Su Kim , Deok-Woo Lee
Abstract: A memory device includes: a memory cell array; a control logic circuit; and a row decoder. The row decoder is configured to activate string selection lines based on control of the control logic circuit. A program interval is formed between a first program operation and a second program operation. The control logic circuit includes a reprogram controller configured to control the row decoder so that a program interval differs in the memory cells connected to different string selection lines among the memory cells connected to a first wordline.
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公开(公告)号：US11049577B2
公开(公告)日：2021-06-29
申请号：US16299684
申请日：2019-03-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seung-Bum Kim , Min-Su Kim , Deok-Woo Lee
Abstract: A memory device includes: a memory cell array; a control logic circuit; and a row decoder. The row decoder is configured to activate string selection lines based on control of the control logic circuit. A program interval is formed between a first program operation and a second program operation. The control logic circuit includes a reprogram controller configured to control the row decoder so that a program interval differs in the memory cells connected to different string selection lines among the memory cells connected to a first wordline.
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公开(公告)号：US11049547B1
公开(公告)日：2021-06-29
申请号：US16986019
申请日：2020-08-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Han-Jun Lee , Seung-Bum Kim , Chul-Bum Kim , Seung-Jae Lee
IPC: G11C11/408 , G11C11/4099 , G11C11/4093 , G11C11/4074 , G11C5/02 , G11C29/02 , G11C29/50
Abstract: A memory device includes multiple word lines. A method of operating the memory device includes: performing a first dummy read operation, with respect to first memory cells connected to a first word line among the word lines, by applying a dummy read voltage, having an offset level of a first level, to the first word line; determining, based on a result of the performing of the first dummy read operation, degradation of a threshold voltage distribution of the first memory cells; adjusting an offset level of the dummy read voltage as a second level, based on a result of the determining of the threshold voltage distribution; and performing a second dummy read operation with respect to second memory cells connected to a second word line among the word lines, by applying a dummy read voltage, having the offset level adjusted as the second level, to the second word line among the word lines.
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19.发明申请公开(公告)号：US20190198514A1
公开(公告)日：2019-06-27
申请号：US16108302
申请日：2018-08-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seung-Bum Kim , Chan-Ho Kim
IPC: H01L27/11551 , H01L27/11578 , G11C5/02 , G11C16/10 , G11C16/34 , G11C29/52 , G11C29/42
Abstract: A nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory blocks, each including a plurality memory cells coupled to word-lines respectively, and the word-lines are stacked vertically on a substrate. The control circuit divides a first memory block of the plurality of memory blocks into a partial bad region and a partial normal region based on error information of an uncorrectable error of the first memory block which is designated as a bad block. The control circuit performs a memory operation on the partial normal region by applying a first bias condition to the partial bad region and by applying a second bias condition to the partial normal region, based on a command and an address, and the first bias condition is different from the second bias condition.
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公开(公告)号：US09953712B2
公开(公告)日：2018-04-24
申请号：US15680104
申请日：2017-08-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Chul Park , Seung-Bum Kim , Myung-Hoon Choi
CPC classification number: G11C16/14 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/3445 , G11C16/3459 , G11C16/3477
Abstract: A nonvolatile memory device includes a memory cell array having memory cells, a row decoder circuit connected to the memory cells through word lines, a page buffer circuit connected to the memory cells through bit lines, and a control circuit controlling the row decoder circuit and the page buffer circuit to repeatedly perform an erase loop including an erase and an erase verification with respect to the memory cells. The control circuit is configured to select one of an increase and a decrease of an erase voltage according to a result of the erase verification of a current erase loop and apply the controlled erase voltage to the memory cells in the erase operation of a subsequent erase loop.
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