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公开(公告)号：US20240231757A9
公开(公告)日：2024-07-11
申请号：US18322837
申请日：2023-05-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Wooseok YI , Soon-Wan KWON , Seungchul JUNG
CPC classification number: G06F7/5443 , G06F7/556
Abstract: A memory device includes: a computing module; and an in-memory computing (IMC) macro comprising: a memory comprising a plurality of bit cells storing pieces of fraction data of a first data set; and an IMC computing module configured to perform an operation between the pieces of fraction data of the first data set read from the memory and pieces of fraction data of a second data set received from an input control module, wherein a plurality of pieces of data included in the first data set share a first exponent, and wherein a plurality of pieces of data included in the second data set share a second exponent.
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公开(公告)号：US20240134606A1
公开(公告)日：2024-04-25
申请号：US18322837
申请日：2023-05-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Wooseok YI , Soon-Wan KWON , Seungchul JUNG
CPC classification number: G06F7/5443 , G06F7/556
Abstract: A memory device includes: a computing module; and an in-memory computing (IMC) macro comprising: a memory comprising a plurality of bit cells storing pieces of fraction data of a first data set; and an IMC computing module configured to perform an operation between the pieces of fraction data of the first data set read from the memory and pieces of fraction data of a second data set received from an input control module, wherein a plurality of pieces of data included in the first data set share a first exponent, and wherein a plurality of pieces of data included in the second data set share a second exponent.
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公开(公告)号：US20220365752A1
公开(公告)日：2022-11-17
申请号：US17542833
申请日：2021-12-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyungwoo LEE , Seungchul JUNG , Sang Joon KIM , Sungmeen MYUNG
Abstract: A multiply-accumulate (MAC) computation circuit includes: a source bit cell block configured to determine a MAC operation result of an input signal based on a plurality of source bit cells; a replica bit cell block comprising a plurality of replica bit cells corresponding to the plurality of source bit cells; and a readout circuit configured to read out a digital value of the MAC operation result using the replica bit cell block.
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公开(公告)号：US20220357922A1
公开(公告)日：2022-11-10
申请号：US17546523
申请日：2021-12-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyungwoo LEE , Sang Joon KIM , Seok Ju YUN , Seungchul JUNG
Abstract: A multiply-accumulate (MAC) computation circuit includes: a bit-cell array configured to generate an analog output corresponding to a MAC operation result of an input signal; a first analog-to-digital conversion (ADC) circuit configured to determine an upper part of a digital output corresponding to the analog output; and a second ADC circuit configured to determine a lower part of the digital output based on a reference voltage corresponding to the upper part.
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公开(公告)号：US20220019884A1
公开(公告)日：2022-01-20
申请号：US17194571
申请日：2021-03-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungchul JUNG , Sangjoon KIM , Sungmeen MYUNG
IPC: G06N3/063 , G11C11/4094
Abstract: A processing device includes: a plurality of bitcells, each of the plurality of bitcells including: a variable resistor layer including a plurality of active variable resistors and a plurality of inactive variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, wherein at least one of the plurality of bitcells includes a via penetrating through the variable resistor layer and connecting at least one of the switches to at least one of the active variable resistors.
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Patent Agency Ranking
公开(公告)号：US20220004852A1
公开(公告)日：2022-01-06
申请号：US17150891
申请日：2021-01-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongmin JU , Sangjoon KIM , Hyungwoo LEE , Seungchul JUNG
IPC: G06N3/063 , G06N3/04 , G11C11/4076 , G11C11/4074
Abstract: An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; and a time-digital converter configured to perform time-digital conversion at the second time points.
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公开(公告)号：US20200382000A1
公开(公告)日：2020-12-03
申请号：US16678021
申请日：2019-11-08
Inventor： Seungchul JUNG , Sang Joon KIM , Junyoung PARK , Yoonmyung LEE , Hyungmin GI
Abstract: A boost converter and a cell applicable to the boost converter are provided. The cell comprises a control circuit configured to generate a bottom control signal related to a bottom plate of a capacitor, and a top control signal related to a top plate of the capacitor to connect the capacitor based on one or more operational phases, and a booster configured to convert the top control signal generated by the control circuit, wherein the capacitor is configured to be sequentially connected to voltage levels through switches, based on the bottom control signal and the converted top control signal.
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18.发明申请公开(公告)号：US20200076298A1
公开(公告)日：2020-03-05
申请号：US16553405
申请日：2019-08-28
Inventor： Seungchul JUNG , Kye-Seok YOON , Gyu-Hyeong CHO , Sang Joon KIM , Sang Jin LIM
Abstract: A single-inductor multiple-output (SIMO) converter includes a converter configured to provide respective voltages of a plurality of channels with a single inductor and a control logic configured to control switches of the converter based on clocks corresponding to the plurality of channels, wherein the control logic is configured to compare an output voltage of a selected channel of the plurality of channels that corresponds to a control target to a reference voltage of the selected channel based on a clock of the selected channel and operate in one of a first mode that adaptively adjusts a number of times that a pulse triggering a power transfer to the channel is generated, and a second mode that blocks a generation of the pulse.
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公开(公告)号：US20240354059A1
公开(公告)日：2024-10-24
申请号：US18761402
申请日：2024-07-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungmeen MYUNG , Sangjoon KIM , Seungchul JUNG
CPC classification number: G06F7/5443 , G01R19/0046 , G06F13/4022 , G06F13/4282 , G06N3/04 , G11C11/161 , G11C11/1673 , G11C11/54
Abstract: A neuromorphic device includes a plurality of resistor lines, each comprising a plurality of resistors that are serially connected to each other; one or more current sources configured to control a current flowing in each of the resistor lines to a respective current value; a plurality of capacitors configured to be electrically connected to each of the resistor lines and to sample respective voltage of each of the resistor lines representing results of neuromorphic operations; and a switch configured to connect the plurality of the capacitors in parallel after the sampling the respective voltage of each of the resistor lines, to output a sum of the results of neuromorphic operations.
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公开(公告)号：US20230170026A1
公开(公告)日：2023-06-01
申请号：US17880849
申请日：2022-08-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seok Ju YUN , Daekun YOON , Sang Joon KIM , Seungchul JUNG
CPC classification number: G11C16/102 , G11C16/32 , G11C16/20 , G11C29/52
Abstract: Provided is method and apparatus with memory array programming. A memory apparatus may include a memory array including memory cells, and a memory controller, where the memory controller is configured to configured to repeat, for a plurality of times, a generation of a first present time current error between a first present time current and a first target current, both of a first memory cell, a generation of a second present time current error between a second present time current and a second target current, both of a second memory cell, where a greatest among the first present time current error and the second present time current error is a greatest present time current error, and a programming of a select one of the first and second memory cells that has the greatest present time current error.
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