公开(公告)号：US09831139B2

公开(公告)日：2017-11-28

申请号：US14997823

申请日：2016-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng Ding ,  Junjung Kim ,  Jeong HOON Ahn

IPC: H01L21/66 ,  G01R31/28 ,  G01R31/26 ,  H01L23/544 ,  H01L21/78

CPC classification number: H01L22/32 ,  G01R31/2644 ,  G01R31/2884 ,  H01L21/78 ,  H01L22/34 ,  H01L23/544 ,  H01L2223/5446

Abstract: A test structure for manufacturing a semiconductor device includes a test element, a first pad connected to the test element, and a second pad connected to the test element. A first wire is connected to the test element, and the first wire and the test element are part of a first layer disposed on a semiconductor substrate. A second wire is connected to the first wire, and is part of a second layer disposed on the semiconductor substrate, and the second layer is different from the first layer.

公开(公告)号：US12014935B2

公开(公告)日：2024-06-18

申请号：US15931738

申请日：2020-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng Ding ,  Jeong Hoon Ahn ,  Yun Ki Choi

IPC: H01L21/311 ,  H01L21/48 ,  H05K3/10 ,  H01L23/64

CPC classification number: H01L21/486 ,  H05K3/107 ,  H01L23/642

Abstract: The method of manufacturing an interposer includes providing a substrate including a first region and a second region adjacent to the first region, forming a first mold structure on the substrate, forming a photoresist layer on the first mold structure, forming a first transfer pattern over the photoresist layer on the first region, using a first photomask, forming a second transfer pattern over the photoresist layer on the second region, using the first photomask, forming a mask pattern on the first mold structure, using the first transfer pattern and the second transfer pattern and forming a first trench and a second trench in the first mold structure, using the mask pattern, the first trench being formed in the first region, and the second trench being formed in the second region.

公开(公告)号：US20240178131A1

公开(公告)日：2024-05-30

申请号：US18382546

申请日：2023-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunoo KIM ,  Shaofeng Ding ,  Jeonghoon Ahn ,  Jaehee Oh

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76813 ,  H01L23/481 ,  H01L23/5283 ,  H01L24/05 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2924/04941

Abstract: A semiconductor device includes: a semiconductor substrate; an integrated circuit layer disposed on the semiconductor substrate; a first metal wiring layer to an n-th metal wiring layer sequentially disposed on the semiconductor substrate and the integrated circuit layer, wherein n is a positive integer; a plurality of wiring vias connecting the first to n-th metal wiring layers to each other, and a through-via extending in a vertical direction from a via connection pad, which is any one of the first metal wiring layer to the n-th metal wiring layer, toward the semiconductor substrate and penetrating the semiconductor substrate, wherein the via connection pad is a capping-type via connection pad formed on an upper surface of the through-via.

公开(公告)号：US11961882B2

公开(公告)日：2024-04-16

申请号：US17472771

申请日：2021-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng Ding ,  Jeong Hoon Ahn ,  Yun Ki Choi

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L49/02

CPC classification number: H01L28/92 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223

Abstract: A semiconductor device includes a semiconductor substrate including a connection region, a pair of epitaxial patterns provided at the semiconductor substrate, a capacitor disposed between the pair of epitaxial patterns, a middle connection layer on the capacitor, an interconnection layer on the middle connection layer, and a through-via provided under the interconnection layer and penetrating the connection region of the semiconductor substrate. The capacitor includes an upper portion of the semiconductor substrate between the pair of epitaxial patterns, a metal electrode on the upper portion of the semiconductor substrate, and a dielectric pattern disposed between the upper portion of the semiconductor substrate and the metal electrode. The through-via is connected to the capacitor through the interconnection layer and the middle connection layer.

公开(公告)号：US11139286B2

公开(公告)日：2021-10-05

申请号：US16569481

申请日：2019-09-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shaofeng Ding

IPC: H01L23/52 ,  H01L23/64 ,  H01L27/01 ,  H01L49/02 ,  H01L23/522

Abstract: According to an example embodiment of the present inventive concept, a semiconductor device includes a substrate. A first insulating layer is disposed on the substrate. A thin-film resistor is disposed in the first insulating layer. A capacitor structure is disposed on the first insulating layer and includes a first electrode pattern, a first dielectric pattern, a second electrode pattern, a second dielectric pattern and a third electrode pattern sequentially stacked. A first via is connected to the first electrode pattern and the third electrode pattern. A part of the first via is disposed in the first insulating layer. A second via is connected to the second electrode pattern, and a third via is connected to the thin-film resistor.

公开(公告)号：US11133266B2

公开(公告)日：2021-09-28

申请号：US16876502

申请日：2020-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng Ding ,  Jeong Hoon Ahn ,  Yun Ki Choi

IPC: H01L23/544 ,  H01L21/48 ,  H01L25/065 ,  H01L25/18 ,  H01L23/498 ,  H01L25/00

Abstract: A method of fabricating a semiconductor device comprises forming first and second align keys in a wafer, the second align key apart from the first align key, forming third and fourth align keys in the wafer, the third align key apart from the second align key, the fourth align key apart from the third align key, forming a fifth align key in the wafer, the fifth align key apart from the fourth align key, forming a first line pattern in the wafer using the second and third align keys, forming a second line pattern in the wafer using the fourth and fifth align keys, forming a first interposer including the first line pattern by cutting a space between the first and second align keys, and forming a second interposer, the second interposer including the second line pattern by cutting a space between the third and fourth align keys.

公开(公告)号：US11094624B2

公开(公告)日：2021-08-17

申请号：US16596074

申请日：2019-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng Ding ,  Jeonghoon Ahn

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/00 ,  H01L49/02 ,  H01L21/768

Abstract: A semiconductor device includes a first electrode disposed on a substrate. A capacitor dielectric layer is on the first electrode. A second electrode is on the capacitor dielectric layer. A first insulating layer is on the first and second electrodes and the capacitor dielectric layer. A first interconnection structure is on the first insulating layer and connected to the first electrode. A second interconnection structure is on the first insulating layer and connected to the second electrode. A second insulating layer is on the first and second interconnection structures. A plurality of connection structures are configured to pass through the second insulating layer and be connected to the first and second interconnection structures. Each of the first and second interconnection structures has an aluminum layer.

公开(公告)号：US11043456B2

公开(公告)日：2021-06-22

申请号：US16660124

申请日：2019-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinho Park ,  Shaofeng Ding ,  Yongseung Bang ,  Jeong Hoon Ahn

IPC: H01L23/535 ,  H01L27/108

Abstract: A semiconductor device includes a substrate, a first electrode including a first hole, a first dielectric layer on an upper surface of the first electrode and on an inner surface of the first hole, a second electrode on the first dielectric layer, a second dielectric layer on the second electrode, a third electrode on the second dielectric layer and including a second hole, and a first contact plug extending through the second electrode and the second dielectric layer and extending through the first hole and the second hole. A sidewall of the first contact plug is isolated from direct contact with the sidewall of the first hole and a sidewall of the second hole, and has a step portion located adjacent to an upper surface of the second electrode.

公开(公告)号：US12199016B2

公开(公告)日：2025-01-14

申请号：US18529096

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng Ding ,  Jeong Hoon Ahn ,  Yun Ki Choi

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/18

Abstract: A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.

公开(公告)号：US20240222421A1

公开(公告)日：2024-07-04

申请号：US18603529

申请日：2024-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihyung KIM ,  Jeonghoon Ahn ,  Jaehee Oh ,  Shaofeng Ding ,  Wonji Park ,  Jegwan Hwang

IPC: H01G4/30 ,  H01L23/522

CPC classification number: H01L28/65 ,  H01L23/5223 ,  H01L28/87

Abstract: A metal-insulator-metal capacitor includes a first electrode disposed in a first region of an upper surface of a substrate, a second electrode covering the first electrode and extending to a second region surrounding an outer periphery of the first region, a third electrode covering the second electrode and extending to a third region surrounding an outer periphery of the second region, a first dielectric layer disposed between the first electrode and the second electrode to cover an upper surface and a side surface of the first electrode and extending to the second region, and a second dielectric layer disposed between the second electrode and the third electrode to cover an upper surface and a side surface of the second electrode and extending to the third region and in contact with the first dielectric layer.