公开(公告)号：US20240203875A1

公开(公告)日：2024-06-20

申请号：US18239504

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiwon KIM ,  Jiyoung KIM ,  Woosung YANG ,  Sukkang SUNG

IPC: H01L23/528 ,  G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H01L23/5283 ,  G11C16/0483 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device including a first semiconductor structure overlapping a second semiconductor structure, the second semiconductor structure having first and second regions and including a plate layer; gate electrodes spaced apart from each other in a first direction; channel structures passing through the gate electrodes; gate separation regions extending in a second direction; first and second upper isolation regions dividing an upper gate electrode into first, second and third sub-gate electrodes between adjacent gate separation regions; and contact plugs extending in the first direction, each of the first and second upper isolation regions has a region extending in a third direction, and the first sub-gate electrode has a first pad region having a first width and a second pad region having a second width narrower than the first width in a fourth direction, and the first sub-gate electrode is connected to one of the contact plugs.

公开(公告)号：US20240114704A1

公开(公告)日：2024-04-04

申请号：US18187803

申请日：2023-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonyoung KWON ,  Jiyoung KIM ,  Woosung YANG ,  Sukkang SUNG

IPC: H10B80/00 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B80/00 ,  H10B43/27 ,  H10B43/40

Abstract: A three-dimensional semiconductor memory device may include a first substrate, a peripheral circuit structure on the first substrate, the peripheral circuit structure including first bonding pads in an upper portion of the peripheral circuit structure, and a cell array structure on the peripheral circuit structure. The cell array structure may include a second substrate, a stack interposed between the peripheral circuit structure and the second substrate, a first insulating layer enclosing the stack, a dummy plug penetrating the first insulating layer, a second insulating layer on the dummy plug, and second bonding pads interposed between the stack and the peripheral circuit structure and connected to the dummy plug. The first bonding pads may contact the second bonding pads, and the dummy plug may be electrically connected to the first bonding pads and the second bonding pads. A top surface of the dummy plug may contact the second insulating layer.

公开(公告)号：US20230005947A1

公开(公告)日：2023-01-05

申请号：US17715508

申请日：2022-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyemin YOO ,  Woosung YANG ,  Sukkang SUNG ,  Ahreum LEE

IPC: H01L27/11573 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11582

Abstract: A semiconductor device includes a first structure having first and second memory regions, an extension region therebetween, and word lines; and a second structure having a circuit region overlapping the extension region. The word lines include first and second common word lines at different levels, and first and second intermediate individual word lines at a same level and spaced apart. Each of the first and second common word lines are in the first and second memory regions and the extension region. The first intermediate individual word line is in the first memory region and extends into the extension region at a level between the first and second common word lines. The second intermediate individual word line is in the second memory region and extends into the extension region. The circuit region includes pass transistors connected to the word lines. A pass transistor overlaps the word lines in the extension region.

公开(公告)号：US20220139855A1

公开(公告)日：2022-05-05

申请号：US17328176

申请日：2021-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min HWANG ,  Jiwon KIM ,  Jaeho AHN ,  Joon-Sung LIM ,  Sukkang SUNG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  G11C16/08 ,  G11C16/10

Abstract: A semiconductor device and electronic system, the device including a cell structure stacked on a peripheral circuit structure, wherein the cell structure includes a first interlayer dielectric layer and first metal pads exposed at the first interlayer dielectric layer and connected to gate electrode layers and channel regions, the peripheral circuit structure includes a second interlayer dielectric layer and second metal pads exposed at the second interlayer dielectric layer and connected to a transistor, the first metal pads include adjacent first and second sub-pads, the second metal pads include adjacent third and fourth sub-pads, the first and third sub-pads are coupled, and a width of the first sub-pad is greater than that of the third sub-pad, and the second sub-pad and the fourth sub-pad are coupled, and a width of the fourth sub-pad is greater than that of the second sub-pad.

公开(公告)号：US20220102334A1

公开(公告)日：2022-03-31

申请号：US17229062

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon KIM ,  Jaeho AHN ,  Sungmin HWANG ,  Joonsung LIM ,  Sukkang SUNG

IPC: H01L25/18 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device includes a first peripheral circuit region comprising a plurality of lower circuitries, a second peripheral circuit region apart from the first peripheral circuit region in a vertical direction, the second peripheral circuit region comprising a plurality of upper circuitries, and a cell region comprising a plurality of word lines, the cell region between the first peripheral circuit region and the second peripheral circuit region in the vertical direction. The plurality of word lines comprise a first word line connected to a first lower circuitry selected from the plurality of lower circuitries and a second word line connected to a first upper circuitry selected from the plurality of upper circuitries.

公开(公告)号：US20250087584A1

公开(公告)日：2025-03-13

申请号：US18666962

申请日：2024-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohyung KIM ,  Chulhae PARK ,  Younghwan SON ,  Sukkang SUNG

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes a first semiconductor structure including, circuit devices on a substrate, a lower interconnection structure, and a capacitor structure on a same level as a level of at least a portion of the lower interconnection structure, and a second semiconductor structure on the first semiconductor structure and including a plurality of memory cells arranged three-dimensionally. The lower interconnection structure includes a lower contact, a lower line on the lower contact, an upper contact on the lower line, and an upper line on the upper contact. The capacitor structure includes first electrode structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, second electrode structures positioned alternately alongside the first electrode structures and spaced apart from each other in the second direction, and dielectric layers between the first electrode structures and the second electrode structures.

公开(公告)号：US20250081457A1

公开(公告)日：2025-03-06

申请号：US18426564

申请日：2024-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongyoon YEO ,  Joonsung KIM ,  Sukkang SUNG ,  Younghwan SON

IPC: H10B43/27 ,  H01L25/065 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device may include a gate stack including conductive patterns and interlayer insulating patterns, which are alternately stacked with each other, a channel layer surrounded by the gate stack, a memory layer surrounding the channel layer, a source structure electrically connected to the channel layer, and an insulating pattern between the memory layer and the source structure. The memory layer and the source structure are spaced apart from each other, and the insulating pattern is in contact with the channel layer, the memory layer, and the source structure.

公开(公告)号：US20240212726A1

公开(公告)日：2024-06-27

申请号：US18544550

申请日：2023-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin SEO ,  Cheonan LEE ,  Sukkang SUNG

IPC: G11C7/10

CPC classification number: G11C7/1048

Abstract: A device includes an input/output circuit, wherein the input/output circuit includes: a control circuit configured to receive a signal indicating whether the device is activated; a variable voltage source configured to generate a variable voltage according to a control operation of the control circuit based on the signal received by the control circuit; an output driver including a first transistor and a second transistor; and a pad configured to output a current that is generated by the output driver, and wherein the variable voltage source is configured to provide the variable voltage to a body of the first transistor and a body of the second transistor.

公开(公告)号：US20240055469A1

公开(公告)日：2024-02-15

申请号：US18305752

申请日：2023-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Bum KIM ,  Cheon An LEE ,  Sukkang SUNG

IPC: H01L21/02 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L28/90 ,  H10B41/10 ,  H10B43/27 ,  H10B41/27 ,  H01L24/08 ,  H10B80/00 ,  H10B43/10 ,  H01L25/0657 ,  H01L2924/1438 ,  H01L2225/06544 ,  H01L2924/1431 ,  H01L2224/08145

Abstract: The present disclosure relates to a semiconductor device, and more particularly, relates to a non-volatile memory device having a three-dimensional structure. The non-volatile memory device according to an embodiment of the present disclosure includes a first chip having a peripheral circuit therein and a second chip that is stacked on the first chip and that includes memory blocks. The second chip includes a common source line that has a plate shape and extends in first and second directions, first and second dummy common source lines disposed at a same height level as the common source line, an upper insulating layer that covers the common source line and the first and second dummy common source lines, and first and second dummy contact plugs extending in a third direction and that are electrically connected to the first and second dummy common source lines, respectively, and used as electrodes of a vertical capacitor.

公开(公告)号：US20230024655A1

公开(公告)日：2023-01-26

申请号：US17858388

申请日：2022-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangdon LEE ,  Joonsung KIM ,  Jiwon KIM ,  Jaeho KIM ,  Sukkang SUNG ,  Jong-Min LEE ,  Euntaek JUNG

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: Disclosed are semiconductor devices and electronic systems including the same. The semiconductor device may include a stack structure extending in a first direction and including gate electrodes vertically stacked on a substrate, selection structures horizontally spaced apart on the stack structure, an upper isolation structure between the selection structure and extending in the first direction on the stack structure, and vertical structures penetrating the stack structure and the selection structures. The vertical structures include first vertical structures arranged along the first direction and penetrating portions of the upper isolation structure. Each selection structure includes a selection gate electrode and a horizontal dielectric pattern that surrounds top, bottom, and sidewall surfaces of the selection gate electrode. Each selection gate electrode includes a line part extending in the first direction, and an electrode part vertically protruding from the line part and surrounding at least a portion of each first vertical structure.