公开(公告)号：US20200043922A1

公开(公告)日：2020-02-06

申请号：US16593058

申请日：2019-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoung Ho Kang ,  Gyeongseop Kim ,  Jeong Lim Kim ,  Jae Myoung Lee ,  Heung Suk Oh ,  Yeon Hwa Lim ,  Joong Won Jeon ,  Sung Min Kim

IPC: H01L27/088 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/033 ,  H01L27/12 ,  H01L21/84

Abstract: A semiconductor device comprises a first fin-type pattern comprising a first long side extending in a first direction, and a first short side extending in a second direction. A second fin-type pattern is arranged substantially parallel to the first fin-type pattern. A first gate electrode intersects the first fin-type pattern and the second fin-type pattern. The second fin-type pattern comprises a protrusion portion that protrudes beyond the first short side of the first fin-type pattern. The first gate electrode overlaps with an end portion of the first fin-type pattern that comprises the first short side of the first fin-type pattern. At least part of a first sidewall of the first fin-type pattern that defines the first short side of the first fin-type pattern is defined by a first trench having a first depth. The first trench directly adjoins a second trench having a second, greater, depth.

公开(公告)号：US10247978B2

公开(公告)日：2019-04-02

申请号：US14962593

申请日：2015-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Min Kim ,  Jeong Dong Noh ,  Jung Woo Hong ,  Jung Hyun Park ,  Duk Jin Jeon

IPC: G02F1/1333 ,  G02F1/1335 ,  G02F1/1345

Abstract: A display apparatus including: a main body having an opening at the front part; a backlight unit configured to generate light; and an image forming unit provided in the front part of the main body, and configured to block or transmit the light generated by the backlight unit to create an image, where the image forming unit includes: a pair of transparent substrates disposed to be opposite to each other; a cable configured to transmit image data to the pair of transparent substrates; and a pair of polarizing films respectively disposed on the outer surfaces of the pair of transparent substrates, and wherein an edge part of at least one transparent substrate of the pair of transparent substrates protrudes to connect to the cable, and at least one polarizing film of the pair of polarizing films extends to the main body in a direction in which the at least one transparent substrate protrudes.

公开(公告)号：US09847245B1

公开(公告)日：2017-12-19

申请号：US15343151

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Kyungseok Oh ,  Sung Min Kim

IPC: H01L21/762 ,  H01L21/306 ,  H01L21/324

CPC classification number: H01L21/76205 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76224

Abstract: A method of filling cavities in a semiconductor structure during fabrication. A layer of a first material, e.g., a polysilazane, is deposited on the semiconductor, and subjected to a first thermal process to change its chemical composition, e.g., to change it to silicon dioxide. It is then etched back, and the cycle of deposition, and thermal processing is repeated. The etch-back may also be repeated in one or more of the cycles after the first cycle, and a second thermal process, that may increase the density of one or more of the deposited layers, may be performed in one or more of the cycles.

公开(公告)号：US20230369332A1

公开(公告)日：2023-11-16

申请号：US18109296

申请日：2023-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Soo Kim ,  Sung Min Kim

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66439

Abstract: There is provided a semiconductor device in which a shape of an isolation layer in a structure in which upper nanosheets are stacked on lower nanosheets is controlled to improve reliability of the device. The semiconductor device includes an active pattern on a substrate and extending in a first direction, lower nanosheets spaced apart from each other in a second direction intersecting the first direction and on the active pattern, an isolation layer on the lower nanosheets and spaced apart from the lower nanosheets in the second direction, upper nanosheets spaced apart from each other in the second direction and on the isolation layer, and a gate electrode on the substrate and surrounding each of the lower nanosheets, the isolation layer, and the upper nanosheets, wherein a sidewall of the isolation layer has a curved shape.

公开(公告)号：US11705435B2

公开(公告)日：2023-07-18

申请号：US17463650

申请日：2021-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Min Kim ,  Dae Won Ha

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80894 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06593

Abstract: A device includes a lower semiconductor substrate, a lower gate structure on the lower semiconductor substrate, the lower gate structure comprises a lower gate electrode, a lower interlayer insulating film on the lower semiconductor substrate, an upper semiconductor substrate on the lower interlayer insulating film, an upper gate structure on the upper semiconductor substrate, and an upper interlayer insulating film on the lower interlayer insulating film, the upper interlayer insulating film covers sidewalls of the upper semiconductor substrate The upper gate structure comprises an upper gate electrode extending in a first direction and gate spacers along sidewalls of the upper gate electrode. The upper gate electrode comprises long sidewalls extending in the first direction and short sidewalls in a second direction The gate spacers are on the long sidewalls of the upper gate electrode and are not disposed on the short sidewalls of the upper gate electrode.

公开(公告)号：US11575014B2

公开(公告)日：2023-02-07

申请号：US17227848

申请日：2021-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deok Han Bae ,  Sung Min Kim ,  Ju Hun Park ,  Myung Yoon Um ,  Jong Mil Youn

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising an element isolation region and an active region defined by the element isolation region, a fin-type pattern on the active region, the fin-type pattern extending in a first horizontal direction, a gate electrode on the fin-type pattern, the gate electrode extending in a second horizontal direction that crosses the first horizontal direction, a capping pattern on the gate electrode, a source/drain region on at least one side of the gate electrode, a source/drain contact on the source/drain region and electrically connected to the source/drain region, and a filling insulating layer on the source/drain contact, the filling insulating layer having a top surface at a same level as a top surface of the capping pattern, and including a material containing a carbon (C) atom.

公开(公告)号：US11139271B2

公开(公告)日：2021-10-05

申请号：US16508857

申请日：2019-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Min Kim ,  Dae Won Ha

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

Abstract: A device includes a lower semiconductor substrate, a lower gate structure on the lower semiconductor substrate, the lower gate structure comprises a lower gate electrode, a lower interlayer insulating film on the lower semiconductor substrate, an upper semiconductor substrate on the lower interlayer insulating film, an upper gate structure on the upper semiconductor substrate, and an upper interlayer insulating film on the lower interlayer insulating film, the upper interlayer insulating film covers sidewalls of the upper semiconductor substrate The upper gate structure comprises an upper gate electrode extending in a first direction and gate spacers along sidewalls of the upper gate electrode. The upper gate electrode comprises long sidewalls extending in the first direction and short sidewalls in a second direction The gate spacers are on the long sidewalls of the upper gate electrode and are not disposed on the short sidewalls of the upper gate electrode.

公开(公告)号：US10923472B2

公开(公告)日：2021-02-16

申请号：US16574887

申请日：2019-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Min Kim ,  Dong Won Kim ,  Geum Jong Bae

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a plurality of fins comprising a first fin, a second fin, a third fin, a fourth fin and a fifth fin, each of the plurality of protruding from the substrate in a first direction, and spaced apart from one another in a second direction that intersects the first direction and a plurality of trenches comprising a first trench, a second trench, a third trench and a fourth trench, each of the plurality of trenches being formed between adjacent fins of the plurality of fins, wherein variation of a first width of the first trench and a third width of the third trench is smaller than a first variation, wherein variation of a second width of the second trench and a fourth width of the fourth trench is smaller than a second variation, and wherein the second variation is greater than the first variation.

公开(公告)号：US20200083377A1

公开(公告)日：2020-03-12

申请号：US16402292

申请日：2019-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Min Kim ,  Hyo Jin Kim ,  Dae Won Ha

IPC: H01L29/78 ,  H01L21/762

Abstract: Semiconductor devices are provided. A semiconductor device includes a fin structure including a stress structure and a semiconductor region that are sequentially stacked on a substrate. The semiconductor device includes a field insulation layer on a portion of the fin structure. The semiconductor device includes a gate electrode on the fin structure. Moreover, the stress structure includes an oxide.

公开(公告)号：US10522364B2

公开(公告)日：2019-12-31

申请号：US16051683

申请日：2018-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Min Kim ,  Dong Won Kim

IPC: H01L21/308 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

Abstract: A method including forming hard mask patterns on a substrate; forming etch stop patterns surrounding the hard mask patterns; forming spacer patterns covering sidewalls of the etch stop patterns; removing the etch stop patterns; etching the substrate to form active and dummy fins; forming a block mask pattern layer surrounding the active and dummy fins and forming mask etch patterns on a top surface of the block mask pattern layer; etching the block mask pattern layer to form block mask patterns surrounding the active fins; etching the dummy fins; removing the block mask patterns surrounding the active fins; and depositing a device isolation film on the substrate such that the device isolation film is not in contact with the upper portions of the active fins, wherein a spacing distance between the active fin and the dummy fin is greater than an active fin spacing distance between the active fins.