公开(公告)号：US20220077110A1

公开(公告)日：2022-03-10

申请号：US17383608

申请日：2021-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoungjoon Kim ,  Sunwon Kang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a substrate, first and second semiconductor chip structures on the substrate and spaced apart from each other in a first horizontal direction, a mold layer on the substrate and covering both the first and second semiconductor chip structures, and a supporting structure on the mold layer and distal from the upper surface of the substrate than both the first and second semiconductor chip structures in a vertical direction. The supporting structure includes first and second supporting portions, spaced apart from each other in a second horizontal direction that is perpendicular to the first horizontal direction and the vertical direction. Each of the first and second supporting portions has a bar shape or a linear shape extending in the first horizontal direction. At least one of the first supporting portion or the second supporting portion overlaps the first and second semiconductor chips in the vertical direction.

公开(公告)号：US11257723B2

公开(公告)日：2022-02-22

申请号：US16698160

申请日：2019-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Do-Hyun Kim ,  Sunwon Kang ,  Hogeon Song ,  Kyung Suk Oh

IPC: H01L23/544 ,  H01L21/18 ,  H01L21/304 ,  H01L21/66 ,  H01L21/67

Abstract: An inspection system for a semiconductor package includes an inspection apparatus that includes a stage on which the semiconductor package is loaded, and a computer coupled to the inspection apparatus. The semiconductor package may include a first semiconductor chip and a second semiconductor chip on the first semiconductor chip, the computer may provide first identification information about the first semiconductor chip and second identification information about the second semiconductor chip, and the computer may control the inspection apparatus to selectively perform a package test process on one of the first and second semiconductor chips, the one of the first and second semiconductor chips being identified as a good chip based on the first identification information and the second identification information.

公开(公告)号：US20140151877A1

公开(公告)日：2014-06-05

申请号：US14175162

申请日：2014-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HWAN-SIK LIM ,  Sunwon Kang ,  Jongho Lee

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05578 ,  H01L2224/0603 ,  H01L2224/06515 ,  H01L2224/13025 ,  H01L2224/13028 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/1411 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a semiconductor chip having a first bump group and a second bump group, and a package substrate having a first pattern for data communication with the semiconductor chip and a second pattern for supplying power to the semiconductor chip or grounding the semiconductor chip, wherein the first bump group is disposed on the first pattern and the second bump group is disposed on the second pattern.

Abstract translation: 半导体封装包括具有第一凸块组和第二凸块组的半导体芯片，以及具有用于与半导体芯片进行数据通信的第一图案的封装基板和用于向半导体芯片供电或将半导体芯片接地的第二图案， 其中所述第一凸块组设置在所述第一图案上，并且所述第二凸块组设置在所述第二图案上。