-
11.发明授权公开(公告)号：US11335673B2
公开(公告)日：2022-05-17
申请号：US16191720
申请日：2018-11-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-Ho Do , Dal-Hee Lee , Jin-Young Lim , Tae-Joong Song , Jong-Hoon Jung
IPC: H01L27/02 , H01L27/118 , G11C5/06 , G06F30/00 , G11C8/16 , G11C11/412 , H01L21/768 , H01L27/088
Abstract: An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.
-
公开(公告)号：US11188704B2
公开(公告)日：2021-11-30
申请号：US16915369
申请日：2020-06-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jin-Tae Kim , Jung-Ho Do , Tae-Joong Song , Doo-Hee Cho , Seung-Young Lee
IPC: G06F30/33 , G06F30/394 , G06F30/392
Abstract: A method of designing an integrated circuit includes receiving input data defining the integrated circuit, receiving information from a standard cell library including a plurality of standard cells, receiving information from a modified cell library including at least one modified cell having a same function as a corresponding standard cell among the plurality of standard cells and having a higher routability than the corresponding standard cell and generating output data by performing placement and routing in response to the input data, the information from the standard cell library and the information from the modified cell library.
-
13.发明授权公开(公告)号：US10990740B2
公开(公告)日：2021-04-27
申请号：US16378751
申请日：2019-04-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jin-Tae Kim , Sung-We Cho , Tae-Joong Song , Seung-Young Lee , Jin-Young Lim
IPC: G06F30/392 , H01L27/02 , G06F30/394 , G06F30/398
Abstract: An integrated circuit may include a first standard cell including first and second active regions extending in a first horizontal direction and a first gate line extending in a second horizontal direction orthogonal to the first horizontal direction; and a second standard cell including third and fourth active regions extending in the first horizontal direction and a second gate line aligned in parallel to the first gate in the second horizontal direction and being adjacent to the first standard cell. A distance between the second active region of the first standard cell and the third active region of the second standard cell may be greater than a distance between the first and second active regions of the first standard cell, and may be greater than a distance between the third and fourth active regions of the second standard cell.
-
公开(公告)号：US20200034508A1
公开(公告)日：2020-01-30
申请号：US16589360
申请日：2019-10-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jung-Ho Do , Jong-Hoon Jung , Seung-Young Lee , Tae-Joong Song
Abstract: An integrated circuit includes: a lower layer including first and second lower patterns extending in a first direction; a first via arranged on the first lower pattern, and a second via arranged on the second lower pattern; a first upper pattern arranged on the first via; and a second upper pattern arranged on the second via, a first color is assigned to the first upper pattern, a second color is assigned to the second upper pattern, the first and second upper patterns are adjacent to each other in a second direction, and the first via is arranged in a first edge region of the first lower pattern, the first edge region being farther away from the second lower pattern than a second edge region of the first lower pattern, the second edge region being opposite to the first edge region.
-
公开(公告)号：US20190311755A1
公开(公告)日：2019-10-10
申请号：US16450035
申请日：2019-06-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Suk-Soo Pyo , Hyun-Taek Jung , Tae-Joong Song
Abstract: A resistive memory device includes: a voltage generator generating a write word line voltage according to activation of a write enable signal; a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output voltage; a word line power path connected to the switch circuit to receive the output voltage; and a word line driver driving a word line according to a voltage applied to the word line power path, wherein a write command starts to be received after a certain delay following the activation of the write enable signal, and a write operation is performed within an activation period of the write enable signal in response to the received write command.
-
Patent Agency Ranking
公开(公告)号：US20180294226A1
公开(公告)日：2018-10-11
申请号：US15946075
申请日：2018-04-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae-Boong Lee , Jung-Ho Do , Tae-Joong Song , Seung-Young Lee , Jong-Hoon Jung , Ji-Su Yu
IPC: H01L23/528 , H01L27/02 , H01L23/522 , H01L21/8234
Abstract: An integrated circuit including: a power rail including first and second conductive lines spaced apart from each other in a vertical direction, wherein the first and second conductive lines extend in parallel to each other in a first horizontal direction, and are electrically connected to each other, to supply power to a first standard cell, wherein the first and second conductive lines are disposed at a boundary of the first standard cell; and a third conductive line between the first and second conductive lines and extending in a second horizontal direction orthogonal to the first horizontal direction, to transfer an input signal or an output signal of the first standard cell.
-
公开(公告)号：US09098670B2
公开(公告)日：2015-08-04
申请号：US14258065
申请日：2014-04-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Tae-Joong Song , Jae-Ho Park , Kwang-Ok Jeong
CPC classification number: G06F17/5072 , G03F1/70 , G03F7/0035 , G06F17/5068 , G06F17/5077
Abstract: A double patterning layout design method includes defining critical paths including a first path and a second path on a schematic circuit, and defining a double patterning layout divided into a first mask layout having a first color and a second mask layout having a second color, the double patterning layout corresponding to the schematic circuit. The defining of the double patterning layout includes anchoring the critical paths on the schematic circuit.
Abstract translation: 双重图案化布局设计方法包括定义包括原理图电路上的第一路径和第二路径的关键路径，以及限定分成具有第一颜色的第一掩模布局和具有第二颜色的第二掩模布局的双图案布局， 双重图案布局对应于原理图电路。 双重图案化布局的定义包括将关键路径锚定在原理图电路上。
-
18.发明授权公开(公告)号：US11955471B2
公开(公告)日：2024-04-09
申请号：US17584930
申请日：2022-01-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-Ho Do , Dal-Hee Lee , Jin-Young Lim , Tae-Joong Song , Jong-Hoon Jung
IPC: H01L27/02 , G06F30/00 , G11C5/06 , G11C8/16 , G11C11/412 , H01L21/768 , H01L27/088 , H01L27/118
CPC classification number: H01L27/0207 , G06F30/00 , G11C5/063 , G11C8/16 , G11C11/412 , H01L21/76895 , H01L27/088 , H01L27/11807 , H01L2027/11875
Abstract: An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.
-
公开(公告)号：US11887914B2
公开(公告)日：2024-01-30
申请号：US18119560
申请日：2023-03-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jung-Ho Do , Tae-Joong Song , Seung-Young Lee , Jong-Hoon Jung
IPC: H01L23/48 , H01L23/482 , H01L27/02 , H01L27/118 , H01L23/485 , H01L21/768 , G06F30/394 , G06F30/392
CPC classification number: H01L23/481 , G06F30/394 , H01L21/76895 , H01L23/482 , H01L23/485 , H01L27/0207 , H01L27/11807 , G06F30/392 , H01L2027/11875
Abstract: An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.
-
公开(公告)号：US10803226B2
公开(公告)日：2020-10-13
申请号：US16589360
申请日：2019-10-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jung-Ho Do , Jong-Hoon Jung , Seung-Young Lee , Tae-Joong Song
IPC: G06F30/392 , G03F7/20 , G03F1/70 , G06F30/20 , G06F30/39 , G06F30/398
Abstract: An integrated circuit includes: a lower layer including first and second lower patterns extending in a first direction; a first via arranged on the first lower pattern, and a second via arranged on the second lower pattern; a first upper pattern arranged on the first via; and a second upper pattern arranged on the second via, a first color is assigned to the first upper pattern, a second color is assigned to the second upper pattern, the first and second upper patterns are adjacent to each other in a second direction, and the first via is arranged in a first edge region of the first lower pattern, the first edge region being farther away from the second lower pattern than a second edge region of the first lower pattern, the second edge region being opposite to the first edge region.
-
-
-
-
-
-
-
-
-
Search Results
36
records
(took 0.015 seconds)
