公开(公告)号：US11189639B2

公开(公告)日：2021-11-30

申请号：US16842867

申请日：2020-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-young Kim ,  Chang-beom Kim ,  Hyun-jeong Roh ,  Tae-joong Song ,  Dal-hee Lee ,  Sung-we Cho

IPC: H01L27/118 ,  H01L27/02

Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.

公开(公告)号：US10573643B2

公开(公告)日：2020-02-25

申请号：US15686795

申请日：2017-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho Do ,  Sang-hoon Baek ,  Tae-joong Song ,  Jong-hoon Jung ,  Seung-young Lee

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/78 ,  H01L27/07 ,  H01L27/02 ,  H01L29/417 ,  H01L23/522 ,  H01L29/08 ,  H01L29/10

Abstract: An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively. The second top active region is over the second through fourth gate lines and insulated from the third gate line. The second top active region forms second and fourth transistors with the second and fourth gate lines respectively.

公开(公告)号：US09852252B2

公开(公告)日：2017-12-26

申请号：US14801239

申请日：2015-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-hoon Baek ,  Tae-joong Song ,  Jae-ho Park ,  Gi-young Yang ,  Jin-tae Kim ,  Hyo-sig Won

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5031 ,  G06F17/5077 ,  G06F2217/84

Abstract: A standard cell library and a method of using the same may include information regarding a plurality of standard cells stored on a non-transitory computer-readable storage medium, wherein at least one of the plurality of standard cells includes a pin through which an input signal or an output signal of the at least one standard cell passes and including first and second regions perpendicular to a stack direction. When the via is disposed in the pin, the second region can provide a resistance value of the via smaller than that of the first region. The standard cell library may further include marker information corresponding to the second region.

公开(公告)号：US09830415B2

公开(公告)日：2017-11-28

申请号：US14799750

申请日：2015-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-kyu Oh ,  Sang-hoon Baek ,  Seung-young Lee ,  Tae-joong Song

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081 ,  G06F2217/82

Abstract: A method of designing a semiconductor integrated circuit (IC) is provided as follows. A standard cell library is generated. The standard cell library includes characteristic information for a plurality of standard cells. The characteristic information includes a characteristic of each standard cell. A characteristic change region is detected. The characteristic change region includes at least one of the plurality of standard cells by comparing characteristics of standard cells to be placed adjacent to the characteristic change region, based on the standard cell library. A characteristic of the at least one standard cell included in the detected characteristic change region is changed to one of the characteristics of the standard cells to be placed adjacent to the characteristic change region to update the standard cell library. A plurality of standard cells of the updated standard cell library is placed.

公开(公告)号：US20160055283A1

公开(公告)日：2016-02-25

申请号：US14799750

申请日：2015-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANG-KYU OH ,  Sang-hoon Baek ,  Seung-young Lee ,  Tae-joong Song

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081 ,  G06F2217/82

Abstract: A method of designing a semiconductor integrated circuit (IC) is provided as follows. A standard cell library is generated. The standard cell library includes characteristic information for a plurality of standard cells. The characteristic information includes a characteristic of each standard cell. A characteristic change region is detected. The characteristic change region includes at least one of the plurality of standard cells by comparing characteristics of standard cells to be placed adjacent to the characteristic change region, based on the standard cell library. A characteristic of the at least one standard cell included in the detected characteristic change region is changed to one of the characteristics of the standard cells to be placed adjacent to the characteristic change region to update the standard cell library. A plurality of standard cells of the updated standard cell library is placed.

Abstract translation: 如下设置半导体集成电路（IC）的设计方法。 生成标准单元库。 标准单元库包括多个标准单元的特征信息。 特征信息包括每个标准单元的特征。 检测到特征变化区域。 基于标准单元库，特征变化区域通过比较与特征变化区域相邻放置的标准单元的特性来包括多个标准单元中的至少一个。 包括在检测到的特征变化区域中的至少一个标准单元的特征被改变为与特征变化区域相邻放置的标准单元的特性之一，以更新标准单元库。 放置更新的标准单元库的多个标准单元。

公开(公告)号：US11042686B2

公开(公告)日：2021-06-22

申请号：US16750501

申请日：2020-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho Do ,  Jong-hoon Jung ,  Ji-Su Yu ,  Seung-young Lee ,  Tae-joong Song ,  Jae-boong Lee

IPC: G06F30/398 ,  H01L27/02 ,  H01L27/118 ,  G06F30/392

Abstract: Provided is an integrated circuit including a plurality of standard cells each including a front-end-of-line (FEOL) region and a back-end-of-line (BEOL) region on the FEOL region, the FEOL region including at least one gate line extending in a first horizontal direction. A BEOL region of a first standard cell among the plurality of standard cells includes an eaves section not overlapping an FEOL region of the first standard cell in a vertical direction, the eaves section protruding in a second horizontal direction perpendicular to the first horizontal direction.

公开(公告)号：US10762958B2

公开(公告)日：2020-09-01

申请号：US16127995

申请日：2018-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suk-soo Pyo ,  Hyun-taek Jung ,  So-hee Hwang ,  Tae-joong Song

IPC: G11C11/16 ,  G11C13/00 ,  G11C11/56

Abstract: A method of controlling a reference cell in a resistive memory to identify values stored in a plurality of memory cells is provided. The method includes writing a first value to the plurality of memory cells, providing, to the reference cell, monotonically increasing or monotonically decreasing reference currents. The method includes reading the plurality of memory cells as each of the reference currents is provided to the reference cell, and determining a read reference current based on an aggregation of results of the reading.

公开(公告)号：US20200235126A1

公开(公告)日：2020-07-23

申请号：US16842867

申请日：2020-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-young KIM ,  Chang-beom Kim ,  Hyun-jeong Roh ,  Tae-joong Song ,  Dal-hee Lee ,  Sung-we Cho

IPC: H01L27/118 ,  H01L27/02

Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.

公开(公告)号：US09436792B2

公开(公告)日：2016-09-06

申请号：US14820983

申请日：2015-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-hoon Baek ,  Tae-joong Song ,  Sang-kyu Oh ,  Seung-young Lee

IPC: G06F17/50 ,  G06F19/00 ,  G21K5/00 ,  G03F1/00

CPC classification number: G06F17/5077 ,  G03F1/00 ,  G06F17/5072 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G21K5/00

Abstract: A method of designing a layout of an integrated chip (IC) includes designing a first layout by place and route a plurality of standard cells that define the IC, and generating a second layout by modifying the first layout during a mask data preparation process related to the first layout, wherein the second layout is generated by connecting first and second patterns from among first layer patterns that correspond to a first layer of the first layout, such that the number of masks necessary for forming the first layer patterns is reduced.

Abstract translation: 设计集成芯片（IC）的布局的方法包括通过放置和布线定义IC的多个标准单元来设计第一布局，以及通过在与...相关的掩模数据准备处理过程中修改第一布局来生成第二布局 第一布局，其中通过连接与第一布局的第一层相对应的第一层图案中的第一和第二图案来生成第二布局，使得形成第一层图案所需的掩模的数量减少。

公开(公告)号：US20160055284A1

公开(公告)日：2016-02-25

申请号：US14801239

申请日：2015-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-hoon Baek ,  Tae-joong Song ,  Jae-ho Park ,  Gi-young Yang ,  Jin-tae Kim ,  Hyo-sig Won

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5031 ,  G06F17/5077 ,  G06F2217/84

Abstract: A standard cell library and a method of using the same may include information regarding a plurality of standard cells stored on a non-transitory computer-readable storage medium, wherein at least one of the plurality of standard cells includes a pin through which an input signal or an output signal of the at least one standard cell passes and including first and second regions perpendicular to a stack direction. When the via is disposed in the pin, the second region can provide a resistance value of the via smaller than that of the first region. The standard cell library may further include marker information corresponding to the second region.

Abstract translation: 标准单元库及其使用方法可以包括关于存储在非暂时计算机可读存储介质上的多个标准单元的信息，其中多个标准单元中的至少一个包括一个引脚，通过该引脚输入信号 或者至少一个标准单元的输出信号通过并包括垂直于堆叠方向的第一和第二区域。 当通孔设置在销中时，第二区域可以提供通孔的电阻值小于第一区域的电阻值。 标准单元库还可以包括对应于第二区域的标记信息。