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11.发明公开公开(公告)号：US20240233857A1
公开(公告)日：2024-07-11
申请号：US18395010
申请日：2023-12-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kuihan Ko , Sang-Won Park , Won-Taeck Jung , Heewon Son , Bongsoon Lim
IPC: G11C29/56
CPC classification number: G11C29/56004 , G11C29/56012 , G11C29/56016 , G11C2029/5602
Abstract: A memory device includes a memory cell array, a reference generating circuit, a row decoding circuit that is connected to the memory cell array through word lines, a page buffer circuit that is connected to the memory cell array through bit lines, a data input/output circuit that is connected to the page buffer circuit through a data line, a buffer circuit, a control logic circuit that performs logic sequences, based on the internal clock signal and the internal power, and a test mode circuit. When the memory device enters a test mode, the test mode circuit disables a part of components of the reference generating circuit. In the test mode, the control logic circuit performs the logic sequences by using an external clock signal provided from an external device.
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公开(公告)号：US12033707B2
公开(公告)日：2024-07-09
申请号：US18301377
申请日：2023-04-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyung-Min Kang , Dongku Kang , Su Chang Jeon , Won-Taeck Jung
CPC classification number: G11C16/3481 , G11C16/08 , G11C16/10 , G11C16/28 , G11C16/30
Abstract: A nonvolatile memory device includes a peripheral circuit region and a memory cell region vertically connected with the peripheral circuit region, the peripheral circuit region including at least one first metal pad, and the memory cell region including at least one second metal pad directly connected with the at least one first metal pad. A method of programming the nonvolatile memory device incudes: receiving a programming command, data for a plurality of pages, and an address corresponding to a selected word-line; programming the data for one of the pages to an unselected word-line; reading data of a previously programmed page from the selected word-line; and programming the data for the remaining pages and the data of the previously programmed page to the selected word-line.
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公开(公告)号：US11742052B2
公开(公告)日：2023-08-29
申请号：US17319493
申请日：2021-05-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Hyun Joo , Tae-Min Park , Hyungsoo Kim , Jaewoo Im , Won-Taeck Jung
IPC: G11C29/50 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/34 , H01L27/11556 , H01L27/11582 , H01L25/065 , H01L25/18 , H01L23/00 , H10B41/27 , H10B43/27
CPC classification number: G11C29/50004 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/3459 , H01L24/08 , H01L25/0657 , H01L25/18 , H10B41/27 , H10B43/27 , G11C2029/5004 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
Abstract: Disclosed is a nonvolatile memory device, which includes a memory cell array including cell strings, a row decoder connected with a ground selection transistor of each of the cell strings through a ground selection line, connected with memory cells of each of the cell strings through word lines, and connected with a string selection transistor of each of the cell strings through a string selection line, and a page buffer connected with the cell strings through bit lines. In a first period of a check operation, the page buffer applies a first bias voltage to the bit lines, and the row decoder applies a turn-off voltage to the ground selection line, a turn-on voltage to the string selection line, and a first check voltage to the word lines. In a second period of the check operation, the page buffer senses first changes of voltages of the bit lines.
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公开(公告)号：US11625302B2
公开(公告)日：2023-04-11
申请号：US16692161
申请日：2019-11-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyung-Min Kang , Dongku Kang , Su Chang Jeon , Won-Taeck Jung
IPC: G11C11/34 , G06F11/14 , G06F11/10 , G06F11/30 , G06F12/0882 , G11C11/56 , G11C11/409 , G11C11/408 , G11C11/4074 , G06F12/0873
Abstract: A method of programming a nonvolatile memory device includes: receiving a programming command, data for a plurality of pages, and an address corresponding to a selected word-line; programming the data for one of the pages to an unselected word-line; reading data of a previously programmed page from the selected word-line; and programming the data for the remaining pages and the data of the previously programmed page to the selected word-line.
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公开(公告)号：US10403363B2
公开(公告)日：2019-09-03
申请号：US15957676
申请日：2018-04-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Won-Taeck Jung
IPC: G06F3/06 , G11C8/08 , G11C16/08 , G11C16/30 , G11C11/56 , G11C16/04 , G11C16/34 , H01L27/1157 , H01L27/11582
Abstract: A nonvolatile memory includes a plurality of memory blocks, a plurality of source drivers corresponding to the plurality of memory blocks, a plurality of pass transistor groups connected between the plurality of source drivers and the plurality of memory blocks, a plurality of block pass transistors connected between a plurality of block word lines and the plurality of pass transistor groups, a plurality of block decoders corresponding to a plurality of memory block groups respectively, and a block pass transistor decoder configured to control voltages of block select lines connected to the plurality of block pass transistors. The plurality of memory blocks are divided into the plurality of memory block groups. Each block decoder is configured to control voltages of block word lines, among the plurality of block word lines, connected to at least two memory blocks of a corresponding memory block group in common.
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Patent Agency Ranking
公开(公告)号：US09449699B2
公开(公告)日：2016-09-20
申请号：US15009856
申请日：2016-01-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Wan Nam , Won-Taeck Jung , Junghoon Park
CPC classification number: G11C16/14 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/3418 , G11C16/344 , G11C16/3445 , H01L27/115
Abstract: An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block.
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公开(公告)号：US12002514B2
公开(公告)日：2024-06-04
申请号：US17706097
申请日：2022-03-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Won Park , Won-Taeck Jung , Han-Jun Lee , Su Chang Jeon
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/3459 , G11C8/12
Abstract: A nonvolatile memory may include; a first memory cell array including a first selection transistor connected to a first string selection line, a second memory cell array including a second selection transistor connected to a second string selection line and spaced apart from the first string selection line by a first cutting line, and a peripheral circuit. The peripheral circuit may provide a first program voltage to the first selection transistor, provide a second program voltage to the second selection transistor different from the first program voltage, program the first selection transistor with a first threshold voltage in response to the first program voltage, and program the second selection transistor with a second threshold voltage level greater than the first threshold voltage in response to the second program voltage.
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18.发明授权公开(公告)号：US11200955B2
公开(公告)日：2021-12-14
申请号：US16734799
申请日：2020-01-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Won-Taeck Jung , Sang-Wan Nam , Jinwoo Park , Jaeyong Jeong
IPC: G11C16/10 , G11C16/20 , G11C16/08 , G11C16/34 , G11C16/04 , H01L27/11582 , H01L27/11524 , H01L27/1157 , H01L27/11556
Abstract: A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.
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19.发明授权公开(公告)号：US09799400B2
公开(公告)日：2017-10-24
申请号：US15203826
申请日：2016-07-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Wan Nam , Won-Taeck Jung
CPC classification number: G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3427
Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.
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公开(公告)号：US09552884B2
公开(公告)日：2017-01-24
申请号：US15238740
申请日：2016-08-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Wan Nam , Won-Taeck Jung , Junghoon Park
CPC classification number: G11C16/14 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/3418 , G11C16/344 , G11C16/3445 , H01L27/115
Abstract: An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block.
Abstract translation: 非易失性存储器的擦除方法包括向衬底提供擦除电压，将选择字线电压提供给与非易失性存储器的存储块内的选定子块相连的字线，将非选择字线电压提供给 在从提供擦除电压的时间点起的第一延迟时间期间，与存储器块内的未选择子块相连的字线，然后浮动与未选择的子块相连的字线。
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