公开(公告)号：US20210383879A1

公开(公告)日：2021-12-09

申请号：US16893859

申请日：2020-06-05

Applicant: SanDisk Technologies LLC

Inventor： Lei Lin ,  Wei Zhao ,  Henry Chin ,  Yen-Lung Li

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/30 ,  G11C16/26 ,  G11C16/08

Abstract: A memory apparatus and method of operation is provided. The apparatus includes selected memory cells coupled to a selected word line and each storing a threshold voltage representative of a selected cell data programmed in a program-verify operation. Unselected memory cells are coupled to a neighbor word line disposed adjacent the selected word line. A control circuit is coupled to the selected and unselected memory cells and configured to ramp from at least one initial voltage applied to the neighbor word line directly to a target neighbor verify voltage without exceeding or falling below the target neighbor verify voltage thereby assisting the selected word line reach at least one verify reference voltage used in verifying the threshold voltage of the selected memory cells during at least one verify stage of the program-verify operation following a program operation of the program-verify operation.

公开(公告)号：US10943917B2

公开(公告)日：2021-03-09

申请号：US16388054

申请日：2019-04-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki Iwai ,  Makoto Koto ,  Sayako Nagamine ,  Ching-Huang Lu ,  Wei Zhao ,  Yanli Zhang ,  James Kai

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L21/762 ,  H01L27/11565 ,  H01L27/11556

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory pillar structures extending through the alternating stack. Each of the memory pillar structures includes a respective memory film and a respective vertical semiconductor channel. Dielectric cores contact an inner sidewall of a respective one of the vertical semiconductor channels. A drain-select-level isolation structure laterally extends along a first horizontal direction and contacts straight sidewalls of the dielectric cores at a respective two-dimensional flat interface. The memory pillar structures may be formed on-pitch as a two-dimensional periodic array, and themay drain-select-level isolation structure may cut through upper portions of the memory pillar structures to minimize areas occupied by the drain-select-level isolation structure.

公开(公告)号：US10770157B1

公开(公告)日：2020-09-08

申请号：US16418642

申请日：2019-05-21

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Wei Zhao ,  Henry Chin

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/10

Abstract: Techniques are described for reducing an injection type of program disturb in a memory device during the pre-charge phase of a program loop. In one approach, a pre-charge voltage on the selected word line and drain side word lines is adjusted based on a risk of the injection type of program disturb. Risk factors such as temperature, WLn position, Vpgm and the selected sub-block, can be used to set the pre-charge voltage to be lower when the risk is higher. In another approach, the pre-charge voltage on the source side word lines is adjusted to reduce a channel gradient and/or the amount of time in which the injection type of program disturb occurs.

公开(公告)号：US20190267096A1

公开(公告)日：2019-08-29

申请号：US15908239

申请日：2018-02-28

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Stanley Jeong ,  Wei Zhao ,  Huai-yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  G11C7/08

Abstract: A circuit includes selected sense circuits configured to be connected to selected bit lines and unselected sense circuits configured to be connected to unselected bit lines during a sense operation. When the sense circuit is connected to the unselected bit line during the sense operation, the sense circuit is locked out in order to reduce current consumption. However, noise from the locked out sense circuit may be transmitted to the sense circuits connected to the selected bit lines through adjacent bit line coupling. In order to reduce the effect of the noise, charge transfer from the sense node may be blocked from passing to the unselected bit lines. Or, charge may be drained from the sense node, thereby preventing the charge from passing to the unselected bit lines.

公开(公告)号：US10249372B2

公开(公告)日：2019-04-02

申请号：US15694008

申请日：2017-09-01

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Wei Zhao ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16

Abstract: A memory device and associated techniques for reducing read disturb of memory cells during a sensing process. Select gate transistors are transitioned to a conductive state one or more time during a sensing process, at the drain and/or source ends of the memory strings in an unselected sub-block. The transitioning can occur periodically, multiple times during the sensing process. When the select gate transistors are in a conductive state, accumulated holes in the channel can be removed. This help provide a faster decrease of the channel potential when the unselected word line voltages are ramped down at the end of the sensing process. The duration of a disturb-inducing channel gradient which is created next to the edge data memory cell is reduced so that read disturb of this cell is also reduced.

公开(公告)号：US11972804B2

公开(公告)日：2024-04-30

申请号：US17846452

申请日：2022-06-22

Applicant: SanDisk Technologies LLC

Inventor： Xuan Tian ,  Henry Chin ,  Liang Li ,  Vincent Yin ,  Wei Zhao ,  Tony Zou

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  G11C29/50 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/349 ,  G11C29/50004 ,  G11C2029/5004 ,  H10B41/27 ,  H10B43/27

Abstract: The memory device includes a memory block with an array of memory cells. The memory device also includes control circuitry that is in communication with the memory cells. The control circuitry is configured to program a group of the memory cells in a programming operation that does not include verify to obtain a natural threshold voltage (nVt) distribution, calculate an nVt width of the nVt distribution, compare the nVt width to a threshold, and identify the memory block as being vulnerable to cross-temperature read errors in response to the nVt width exceeding the threshold.

公开(公告)号：US10685979B1

公开(公告)日：2020-06-16

申请号：US16267625

申请日：2019-02-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ching-Huang Lu ,  Wei Zhao ,  Yanli Zhang ,  James Kai

IPC: H01L29/792 ,  H01L21/4763 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/06 ,  H01L21/768 ,  H01L21/311 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526

Abstract: Electrical isolation between adjacent stripes of drain-select-level electrically conductive layers can be provided by forming a drain-select-level isolation structure between neighboring rows of memory stack structures. The drain-select-level isolation structure can partially cut through upper regions of the neighboring rows of memory stack structures. Vertical semiconductor channels of the neighboring rows of memory stack structures include a lower tubular segment and an upper semi-tubular segment that contact the drain-select-level isolation structure. Electrical current through drain select levels is limited to the semi-tubular segment of each vertical semiconductor channel. Alternatively, the drain-select-level isolation structure can be formed around the memory stack structures within the neighboring rows of memory stack structures. Ion implantation can be used to suppress conduction of electrical current through portions of vertical semiconductor channels that are proximal to the drain-select-level isolation structure.

公开(公告)号：US10068651B1

公开(公告)日：2018-09-04

申请号：US15621215

申请日：2017-06-13

Applicant: SanDisk Technologies LLC

Inventor： Vinh Diep ,  Wei Zhao ,  Ashish Baraskar ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/14 ,  G11C16/24 ,  G11C16/04

Abstract: A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation. A pre-charge operation occurs in which a channel voltage is increased to a positive level. This reduces a channel gradient which can lead to a disturb of the select gate transistors. One approach involves applying a voltage at an intermediate level to the source and/or drain ends of the memory strings, before increasing the voltage from the intermediate level to a peak erase level. Another approach involves driving the word line voltages at a negative level and then at a higher level to down couple and then up couple the channel voltages. The techniques may be adjusted depending on whether the word lines are at a positive floating voltage at a start of the erase operation, and based on a level of the floating voltage.

公开(公告)号：US20230410920A1

公开(公告)日：2023-12-21

申请号：US17845430

申请日：2022-06-21

Applicant: SanDisk Technologies LLC

Inventor： Han-Ping Chen ,  Wei Zhao ,  Henry Chin

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/3436 ,  G11C16/102 ,  G11C16/26 ,  G11C16/08

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected word lines. The memory cells are disposed in strings and configured to retain a threshold voltage. A control means is configured to apply a program voltage to selected ones of the word lines while applying pass voltages to unselected ones of the word lines and ramp down both the selected ones of the plurality of word lines and the unselected ones of the word lines to a recovery voltage at a start of a verify phase of each of a plurality of program loops and apply a targeted word line bias to each of the word lines during the verify phase. The control means is also configured to adjust the recovery voltage based on the targeted word line bias applied to each of the plurality of word lines during the verify phase.

公开(公告)号：US20230410901A1

公开(公告)日：2023-12-21

申请号：US17752524

申请日：2022-05-24

Applicant: SanDisk Technologies LLC

Inventor： Dong-Il Moon ,  Abhijith Prakash ,  Wei Zhao ,  Henry Chin

IPC: G11C11/56 ,  G11C16/26

CPC classification number: G11C11/5642 ,  G11C16/26 ,  G11C11/5671

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the strings and is configured to apply a read voltage to a selected ones of the plurality of word lines during a read operation and ramp down to a discharge voltage at an end of the read operation and apply a ready voltage to the selected ones of the plurality of word lines during a ready period of time following the read operation. The control means is also configured to adjust at least one of the discharge voltage and the ready voltage based on a temperature of the memory apparatus.