公开(公告)号：US5920086A

公开(公告)日：1999-07-06

申请号：US972980

申请日：1997-11-19

Applicant: Roger Morton MacFarlane ,  James Anthony Misewich ,  Sanjay Sethi ,  Sandip Tiwari

Inventor： Roger Morton MacFarlane ,  James Anthony Misewich ,  Sanjay Sethi ,  Sandip Tiwari

IPC: H01L33/26 ,  H05B33/14 ,  H01L33/00

CPC classification number: H01L33/26

Abstract: A device for generating radiant energy comprising a first electrode, a second electrode spaced apart from said first electrode, a material disposed between and in electrical communication with first and second electrodes, which emits radiant energy upon activation. This material is a rare earth metal oxide or a rare earth metal halide.

Abstract translation: 一种用于产生辐射能的装置，包括第一电极，与所述第一电极间隔开的第二电极，设置在第一和第二电极之间并与之电连通的材料，其在激活时发射辐射能。 该材料是稀土金属氧化物或稀土金属卤化物。

公开(公告)号：US5508543A

公开(公告)日：1996-04-16

申请号：US236751

申请日：1994-04-29

Applicant: Allan M. Hartstein ,  Michael A. Tischler ,  Sandip Tiwari

Inventor： Allan M. Hartstein ,  Michael A. Tischler ,  Sandip Tiwari

IPC: H01L21/8247 ,  H01L29/49 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC classification number: H01L29/4975 ,  H01L29/49 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/7883

Abstract: A floating gate is inserted into the gate stack of an EEPROM cell. For an N channel EEPROM device, the floating gate is composed of a material having a conduction band edge (or fermi energy in the case of a metal or composite that includes a metal) at least one and preferably several kT electron volts below the conduction band edge of the channel region. The floating gate material thus has a larger electron affinity than the material of the channel region. This allows the insulator separating the floating gate and the channel to be made suitable thin (less than 100 angstroms) to reduce the writing voltage and to increase the number of write cycles that can be done without failure, without having charge stored on the floating gate tunnel back out to the channel region during read operations. For a P channel EEPROM device, the floating gate is composed of a material having a valence band edge (or fermi energy in the case of a metal or a composite that includes a metal) at least one and preferably several kT (eV) above the valence band edge of the channel region.

Abstract translation: 浮动栅极插入EEPROM单元的栅极堆叠中。 对于N沟道EEPROM器件，浮置栅极由具有导带边缘的材料（或在包含金属的金属或复合材料的情况下的费米能量）组成，其至少一个且优选地在导带之下几个kT电子伏特 通道区域的边缘。 浮栅材料因此具有比沟道区的材料更大的电子亲和力。 这允许将浮动栅极和沟道分离成绝缘体（小于100埃）以减小写入电压并增加可以在没有故障的情况下完成的写入周期数，而不会在浮置栅极上存储电荷 在读取操作期间隧道返回到通道区域。 对于P沟道EEPROM器件，浮动栅极由具有价带边缘（或金属或包含金属的复合材料的情况下的费米能量）的材料组成，至少一个且优选地几个kT（eV） 通道区域的价带边缘。

公开(公告)号：US4987095A

公开(公告)日：1991-01-22

申请号：US207700

申请日：1988-06-15

Applicant: John Batey ,  Sandip Tiwari ,  Steven L. Wright

Inventor： John Batey ,  Sandip Tiwari ,  Steven L. Wright

IPC: H01L29/78 ,  H01L21/203 ,  H01L21/205 ,  H01L21/28 ,  H01L21/31 ,  H01L21/314 ,  H01L21/336 ,  H01L29/267 ,  H01L29/43

CPC classification number: H01L29/66522 ,  H01L21/28264 ,  H01L21/314 ,  H01L29/267 ,  H01L29/432 ,  Y10S148/149 ,  Y10S438/933 ,  Y10S438/958

Abstract: Unpinned epitaxial metal-oxide-compound semiconductor structures are disclosed and a method of fabricating such structures is described. Epitaxial layers of compound semiconductor are grown by MBE which result in the formation of a smooth surface having a stabilized reconstruction. An elemental semiconductor layer is deposited epitaxially in-situ with the compound semiconductor layer which unpins the surface Fermi level. A layer of insulator material is then deposited on the elemental semiconductor layer by PECVD. In one embodiment, the compound semiconductor is GaAs and the elemental semiconductor is Si. The insulator material is a layer of high quality SiO.sub.2. A metal gate is deposited on the SiO.sub.2 layer to form an MOS device. The epitaxial GaAs layer has a density of states which permits the interface Fermi level to be moved through the entire forbidden energy gap. In another embodiment, the SiO.sub.2 deposition completely consumes the interface Si layer so that the resulting MOS device comprises SiO.sub.2 directly overlying the GaAs layer.

公开(公告)号：US4849802A

公开(公告)日：1989-07-18

申请号：US233851

申请日：1988-08-16

Applicant: Thomas N. Jackson ,  Masanori Murakami ,  William H. Price ,  Sandip Tiwari ,  Jerry M. Woodall ,  Steven L. Wright

Inventor： Thomas N. Jackson ,  Masanori Murakami ,  William H. Price ,  Sandip Tiwari ,  Jerry M. Woodall ,  Steven L. Wright

IPC: H01L29/45

CPC classification number: H01L29/452

Abstract: In a semiconductor device, a contact with low resistance to a III-V compound semiconductor substrate was fabricated using refractory materials and small amounts of indium as the contact material. The contact material was formed by depositing Mo, Ge and W with small amounts of In onto doped GaAs wafers. The contact resistance less than 1.0 ohm millimeter was obtained after annealing at 800.degree. C. and the resistance did not increase after subsequent prolonged annealing at 400.degree. C.

Abstract translation: 在半导体器件中，使用耐火材料和少量的铟作为接触材料制造具有低耐III-V化合物半导体衬底的接触。 通过将Mo，Ge和W与少量的In沉积到掺杂的GaAs晶片上形成接触材料。 800℃退火后获得小于1.0欧姆毫米的接触电阻，在400℃下经过长时间的退火后，电阻不增加。

公开(公告)号：US08987701B2

公开(公告)日：2015-03-24

申请号：US13322379

申请日：2010-05-28

Applicant: Sandip Tiwari ,  Ravishankar Sundararaman ,  Sang Hyeon Lee ,  Moonkyung Kim

Inventor： Sandip Tiwari ,  Ravishankar Sundararaman ,  Sang Hyeon Lee ,  Moonkyung Kim

IPC: H01L47/00 ,  H01L29/68 ,  H01L29/51

CPC classification number: H01L29/685 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

Abstract: In one embodiment there is set forth a method comprising providing a semiconductor structure having an electrode, wherein the providing includes providing a phase transition material region and wherein the method further includes imparting energy to the phase transition material region to induce a phase transition of the phase transition material region. By inducing a phase transition of the phase transition material region, a state of the semiconductor structure can be changed. There is further set forth an apparatus comprising a structure including an electrode and a phase transition material region, wherein the apparatus is operative for imparting energy to the phase transition material region to induce a phase transition of the phase transition material region without the phase transition of the phase transition material region being dependent on electron transport through the phase transition material region.

Abstract translation: 在一个实施例中，提出了一种方法，包括提供具有电极的半导体结构，其中所述提供包括提供相变材料区域，并且其中所述方法还包括赋予相变材料区域能量以引起相位的相变 过渡材料区域。 通过引起相变材料区域的相变，可以改变半导体结构的状态。 还提出了一种装置，其包括包括电极和相变材料区域的结构，其中该装置可操作以将能量传递给相变材料区域，以引起相变材料区域的相变而不发生相变 相变材料区域依赖于通过相变材料区域的电子传输。

公开(公告)号：US08553455B2

公开(公告)日：2013-10-08

申请号：US11528712

申请日：2006-09-27

Applicant: Sandip Tiwari ,  Chung Woo Kim

Inventor： Sandip Tiwari ,  Chung Woo Kim

IPC: G11C11/34

CPC classification number: H01L27/115 ,  B81B3/0072 ,  B81B2201/016 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/025 ,  G11C23/00 ,  G11C2213/14 ,  G11C2213/17 ,  G11C2213/77 ,  H01H9/547 ,  H01H59/0009 ,  H01H61/0107 ,  H01L21/28273 ,  H01L27/112 ,  H01L29/66825 ,  H01L29/785

Abstract: Mechanical devices having bistable positions are utilized to form switches and memory devices. The devices are actuatable to different positions and may be coupled to a transistor device in various configurations to provide memory devices. Actuation mechanisms include electrostatic methods and heat. In one form, the mechanical device forms a gate for a field effect transistor. In a further form, the device may be a switch that may be coupled to the transistor in various manners to affect its electrical characteristics when on and off. The memory switch in one embodiment comprises side walls formed with tensile or compressive films. A cross point switch is formed from a plurality of intersecting conductive rows and columns of conductors. Actuatable switches are positioned between each intersection of the rows and columns such that each intersection is independently addressable.

Abstract translation: 利用具有双稳态位置的机械装置来形成开关和存储装置。 这些器件可被驱动到不同的位置，并且可以以各种配置耦合到晶体管器件以提供存储器件。 致动机制包括静电法和热量。 在一种形式中，机械装置形成用于场效应晶体管的栅极。 在另一种形式中，器件可以是开关，其可以以各种方式耦合到晶体管，以便在接通和断开时影响其电特性。 在一个实施例中的存储器开关包括由拉伸或压缩膜形成的侧壁。 交叉点开关由多个交叉的导电行和导体列形成。 可执行开关位于行和列的每个交叉点之间，使得每个交叉点可独立寻址。

公开(公告)号：US06953958B2

公开(公告)日：2005-10-11

申请号：US10393515

申请日：2003-03-19

Applicant: Gregory T. Baxter ,  Sandip Tiwari

Inventor： Gregory T. Baxter ,  Sandip Tiwari

IPC: G11C11/54 ,  G11C13/02 ,  H01L23/58

CPC classification number: G11C13/0014 ,  B82Y10/00 ,  G11C11/54 ,  G11C13/02 ,  G11C2216/08 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A gated metal oxide semiconductor field effect transistor (MOSFET) gain cell is formed with a flow channel for molecule flow. The flow channel is formed under the gate, and between a source and drain of the transistor. The molecule flow modulates a gain of the transistor. Current flowing between the source and drain is representative of charges on the molecules flowing through the flow channel. A plurality of individually addressable gain cells are coupled between chambers containing samples to measure charges on molecules in the samples passing through the gain cells.

Abstract translation: 栅极金属氧化物半导体场效应晶体管（MOSFET）增益单元形成有用于分子流的流动通道。 流通道形成在栅极下方，并在晶体管的源极和漏极之间。 分子流调制晶体管的增益。 在源极和漏极之间流动的电流代表流过流动通道的分子上的电荷。 多个可单独寻址的增益单元耦合在包含样本的室之间以测量通过增益单元的样品中的分子上的电荷。

公开(公告)号：US06316309B1

公开(公告)日：2001-11-13

申请号：US09626332

申请日：2000-07-26

Applicant: Steven John Holmes ,  Howard Leo Kalter ,  Sandip Tiwari ,  Jeffrey John Welser

Inventor： Steven John Holmes ,  Howard Leo Kalter ,  Sandip Tiwari ,  Jeffrey John Welser

IPC: H01L218242

CPC classification number: H01L27/10864 ,  H01L27/10823 ,  H01L27/1087 ,  H01L29/945

Abstract: A densely packed array of vertical semiconductor devices, having pillars, deep trench capacitors, vertical transistors, and methods of making thereof are disclosed. The pillars act as transistor channels, and may be formed utilizing the application of hybrid resist over a block of semiconductor material. Drain doped regions are formed on the top of each pillar. The source doped regions and the plate doped regions are self-aligned and are created by diffusion in the trenches surrounding the pillars. The array has columns of bitlines and rows of wordlines. The capacitors are formed by isolating n+ polysilicon in trenches separating said pillars. The array is suitable for GBit DRAM applications because the deep trench capacitors do not increase array area. The array may have an open bitline architecture, where the plate region is common to all the storage nodes or a folded architecture with two wordlines that pass through each cell having stacked transistors, where one wordline is active and the other is passing for each cell.

Abstract translation: 公开了一种密集堆叠的垂直半导体器件阵列，具有支柱，深沟槽电容器，垂直晶体管及其制造方法。 支柱用作晶体管通道，并且可以利用在半导体材料块上施加混合抗蚀剂来形成。 在每个支柱的顶部形成漏极掺杂区域。 源掺杂区域和板掺杂区域是自对准的，并且通过在柱子周围的沟槽中的扩散而产生。 该阵列具有位线和字线行。 通过在分离所述柱的沟槽中隔离n +多晶硅来形成电容器。 该阵列适用于GBit DRAM应用，因为深沟槽电容器不增加阵列面积。 阵列可以具有开放的位线架构，其中板区域对于所有存储节点是公共的，或者具有两个字线的折叠结构，其中两个字线通过具有堆叠晶体管的每个单元，其中一个字线是活动的，而另一个字线通过每个单元。

公开(公告)号：US06281551B1

公开(公告)日：2001-08-28

申请号：US09369928

申请日：1999-08-09

Applicant: Kevin Kok Chan ,  Christopher Peter D'Emic ,  Erin Catherine Jones ,  Paul Michael Solomon ,  Sandip Tiwari

Inventor： Kevin Kok Chan ,  Christopher Peter D'Emic ,  Erin Catherine Jones ,  Paul Michael Solomon ,  Sandip Tiwari

IPC: H01L2701

CPC classification number: H01L21/76251

Abstract: A back-plane for a semiconductor device, includes an oxidized substrate, a metal film formed on the oxidized substrate forming a back-gate, a back-gate oxide formed on the back-gate, and a silicon layer formed on the back-gate oxide.

Abstract translation: 用于半导体器件的背板包括氧化的衬底，形成在形成背栅的氧化衬底上的金属膜，形成在背栅上的背栅氧化物和形成在背栅上的硅层 氧化物。

公开(公告)号：US06236060B1

公开(公告)日：2001-05-22

申请号：US08974215

申请日：1997-11-19

Applicant: Kevin Kok Chan ,  Sandip Tiwari

Inventor： Kevin Kok Chan ,  Sandip Tiwari

IPC: H01L2906

CPC classification number: H01L33/08

Abstract: A light emitting device is disclosed comprising a bottom layer of electrically conductive material. A block of electrically insulating material is disposed on the bottom layer. At least a portion of the block is optically transparent. A top layer of electrically conductive material is disposed on the block. A plurality of discrete nano-crystals of a material selected from the group consisting of Group IV, Group III-V, and Group II-VI is disposed within the block, and are thereby electrically insulated from the top and bottom layers. Also provided are bottom and top electrodes connected to the bottom and top layers, respectively, for applying a voltage therebetween.

Abstract translation: 公开了一种发光器件，其包括导电材料的底层。 一层电绝缘材料设置在底层上。 块的至少一部分是光学透明的。 导电材料的顶层设置在块上。 选自由组IV，组III-V和组II-VI组成的组的材料的多个离散纳米晶体设置在所述块内，并且由此与顶层和底层电绝缘。 还提供了分别连接到底层和顶层的底部和顶部电极，用于在它们之间施加电压。