公开(公告)号：US08786028B2

公开(公告)日：2014-07-22

申请号：US13445667

申请日：2012-04-12

申请人： Hyung-Seok Hong ,  Sang-Jin Hyun ,  Hong-Bae Park ,  Hoon-Joo Na ,  Hye-Lan Lee

发明人： Hyung-Seok Hong ,  Sang-Jin Hyun ,  Hong-Bae Park ,  Hoon-Joo Na ,  Hye-Lan Lee

IPC分类号： H01L27/088

CPC分类号： H01L21/823437 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： A method of manufacturing a semiconductor device, a semiconductor device and systems incorporating the same include transistors having a gate metal doped with impurities. An altered work function of the transistor may alter a threshold voltage of the transistor. In certain embodiments, a gate metal of a first MOSFET is doped with impurities. A gate metal of a second MOSFET may be left undoped, doped with the same impurities with a different concentration, and/or doped with different impurities. In some embodiments, the MOSFETs are FinFETs, and the doping may be a conformal doping.

摘要翻译： 制造半导体器件的方法，半导体器件和结合其的系统包括掺杂有杂质的栅极金属的晶体管。 晶体管的改变的功函数可以改变晶体管的阈值电压。 在某些实施例中，第一MOSFET的栅极金属掺杂有杂质。 第二MOSFET的栅极金属可以不掺杂，掺杂有不同浓度的相同杂质和/或掺杂有不同杂质。 在一些实施例中，MOSFET是FinFET，并且掺杂可以是共形掺杂。

公开(公告)号：US08580629B2

公开(公告)日：2013-11-12

申请号：US13241871

申请日：2011-09-23

申请人： Hong-Bae Park ,  Sang-Jin Hyun ,  Hu-Yong Lee ,  Hoon-Joo Na ,  Jeong-Hee Han ,  Hye-Lan Lee ,  Hyung-Seok Hong

发明人： Hong-Bae Park ,  Sang-Jin Hyun ,  Hu-Yong Lee ,  Hoon-Joo Na ,  Jeong-Hee Han ,  Hye-Lan Lee ,  Hyung-Seok Hong

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/28185 ,  H01L21/28202 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545

摘要： A method of fabricating a semiconductor device may include: preparing a substrate in which first and second regions are defined; forming an interlayer insulating film, which includes first and second trenches, on the substrate; forming a work function control film, which contains Al and N, along a top surface of the interlayer insulating film, side and bottom surfaces of the first trench, and side and bottom surfaces of the second trench; forming a mask pattern on the work function control film formed in the second region; injecting a work function control material into the work function control film formed in the first region to control a work function of the work function control film formed in the first region; removing the mask pattern; and forming a first metal gate electrode to fill the first trench and forming a second metal gate electrode to fill the second trench.

摘要翻译： 制造半导体器件的方法可以包括：制备其中限定了第一和第二区域的衬底; 在衬底上形成包括第一和第二沟槽的层间绝缘膜; 沿着层间绝缘膜的上表面，第一沟槽的侧表面和底表面以及第二沟槽的侧表面和底表面形成包含Al和N的功函数控制膜; 在形成在第二区域中的功函数控制膜上形成掩模图案; 将工作功能控制材料注入到形成在第一区域中的功函数控制膜中，以控制形成在第一区域中的功函数控制膜的功函数; 去除掩模图案; 以及形成第一金属栅电极以填充所述第一沟槽并形成第二金属栅电极以填充所述第二沟槽。

公开(公告)号：US09287199B2

公开(公告)日：2016-03-15

申请号：US12972961

申请日：2010-12-20

申请人： Hye-Lan Lee ,  Hong-Bae Park ,  Sang-Jin Hyun ,  Yu-Gyun Shin ,  Sug-Hun Hong ,  Hoon-Joo Na ,  Hyung-Seok Hong

发明人： Hye-Lan Lee ,  Hong-Bae Park ,  Sang-Jin Hyun ,  Yu-Gyun Shin ,  Sug-Hun Hong ,  Hoon-Joo Na ,  Hyung-Seok Hong

IPC分类号： H01L23/522 ,  H01L23/485 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/08 ,  H01L29/94

CPC分类号： H01L27/092 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0811 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.

摘要翻译： 提供了CMOS晶体管，具有晶体管的半导体器件和具有该器件的半导体模块。 CMOS晶体管可以包括分别设置在半导体衬底的第一和第二区域中的第一和第二互连结构。 半导体衬底的第一和第二区域可以具有不同的导电类型。 第一和第二互连结构可以设置在半导体衬底上。 第一互连结构可以具有与第二互连结构不同的堆叠结构。 CMOS晶体管可以设置在半导体器件中。 半导体器件可以设置在半导体模块中。

公开(公告)号：US09553094B2

公开(公告)日：2017-01-24

申请号：US15069920

申请日：2016-03-14

申请人： Wei-Hsiung Tseng ,  Ju-Youn Kim ,  Seok-Jun Won ,  Jong-Ho Lee ,  Hye-Lan Lee ,  Yong-Ho Ha

发明人： Wei-Hsiung Tseng ,  Ju-Youn Kim ,  Seok-Jun Won ,  Jong-Ho Lee ,  Hye-Lan Lee ,  Yong-Ho Ha

IPC分类号： H01L27/092 ,  H01L29/49 ,  H01L29/43

CPC分类号： H01L27/0924 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/845 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848

摘要： Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在衬底上形成层间绝缘层，所述层间绝缘层包括第一沟槽; 在第一沟槽中形成高k电介质层; 在高k电介质层上依次形成扩散层和阻挡层; 随后进行退火; 退火后，依次去除阻挡层和扩散层; 在高k电介质层上形成第一阻挡层; 在第一阻挡层上依次形成功函数调整层和栅极导体; 并在栅极导体上形成覆盖层。

公开(公告)号：US20060226470A1

公开(公告)日：2006-10-12

申请号：US11400243

申请日：2006-04-10

申请人： Hag-Ju Cho ,  Taek-Soo Jeon ,  Hye-Lan Lee ,  Sang-Bom Kang ,  Yu-Gyun Shin

发明人： Hag-Ju Cho ,  Taek-Soo Jeon ,  Hye-Lan Lee ,  Sang-Bom Kang ,  Yu-Gyun Shin

IPC分类号： H01L29/788 ,  H01L29/76 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A semiconductor device comprising a semiconductor substrate having a first impurity region and a second impurity region, a first gate pattern formed on the first impurity region, and a second gate pattern formed on the second impurity region is disclosed. The first gate pattern comprises a first gate insulation layer pattern, a metal layer pattern having a first thickness, and a first polysilicon layer pattern. The second gate pattern comprises a second gate insulation layer pattern, a metal silicide layer pattern having a second thickness smaller than the first thickness, and a second polysilicon layer pattern. The metal silicide layer pattern is formed from a material substantially the same as the material from which the metal layer pattern is formed. A method for manufacturing the semiconductor device is also disclosed.

公开(公告)号：US20140374840A1

公开(公告)日：2014-12-25

申请号：US14312109

申请日：2014-06-23

申请人： Hye-Lan Lee ,  Sang-Bom Kang ,  Jae-Jung Kim ,  Moon-Kyu Park ,  Jae-Yeol Song ,  June-Hee Lee ,  Yong-Ho Ha ,  Sang-Jin Hyun

发明人： Hye-Lan Lee ,  Sang-Bom Kang ,  Jae-Jung Kim ,  Moon-Kyu Park ,  Jae-Yeol Song ,  June-Hee Lee ,  Yong-Ho Ha ,  Sang-Jin Hyun

IPC分类号： H01L27/088

CPC分类号： H01L27/0886 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

摘要： A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.

摘要翻译： 半导体器件包括衬底和衬底上的第一和第二栅电极。 第一栅极电极包括第一栅极绝缘膜，该第一栅极绝缘膜具有在基板上的底部部分以及侧壁部分，其从底部延伸并远离基板限定具有第一宽度的第一沟槽和填充第一沟槽的第一功能膜。 所述第二栅电极包括第二栅极绝缘膜，所述第二栅极绝缘膜具有在所述基板上的底部部分和从所述底部部分延伸的侧壁部分，所述侧壁部分限定具有不同于所述第一宽度的第二宽度的第二沟槽;第二功能膜， 在第二沟槽中并且限定第三沟槽，以及第三沟槽中的金属区域。 第一宽度可以小于第二宽度。

公开(公告)号：US20070026596A1

公开(公告)日：2007-02-01

申请号：US11492400

申请日：2006-07-25

申请人： Hag-Ju Cho ,  Taek-Soo Jeon ,  Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang

发明人： Hag-Ju Cho ,  Taek-Soo Jeon ,  Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang

IPC分类号： H01L21/8234

CPC分类号： H01L21/823828 ,  H01L21/823835 ,  H01L21/823842

摘要： In a gate structure and a method of forming the same, a first conductive pattern is formed on a substrate and comprises a metal-containing material. A second conductive pattern is formed on the first conductive pattern, and the second conductive pattern comprises metal and silicon. A third conductive pattern is formed on the second conductive pattern, and the third conductive pattern comprises polysilicon. A gate conductive pattern of an n-type metal-oxide semiconductor (NMOS) transistor, a p-type MOS (PMOS) transistor and a complementary MOS (CMOS) transistor includes the gate structure. The second conductive pattern is interposed between the first and third conductive patterns and the third conductive pattern is prevented from making direct contact with the first conductive pattern, so that polysilicon in the third conductive pattern is sufficiently prevented from being chemically reacted with the metal in the first conductive pattern in advance, thereby improving electrical characteristics of the transistor.

摘要翻译： 在栅极结构及其形成方法中，第一导电图案形成在基板上并且包括含金属的材料。 在第一导电图案上形成第二导电图案，并且第二导电图案包括金属和硅。 在第二导电图案上形成第三导电图案，并且第三导电图案包括多晶硅。 n型金属氧化物半导体（NMOS）晶体管，p型MOS（PMOS）晶体管和互补MOS（CMOS）晶体管的栅极导电图案包括栅极结构。 第二导电图案插入在第一和第三导电图案之间，并且防止第三导电图案与第一导电图案直接接触，使得充分防止第三导电图案中的多晶硅与金属在化学反应中 第一导电图案，从而改善晶体管的电特性。

公开(公告)号：US20060273344A1

公开(公告)日：2006-12-07

申请号：US11400560

申请日：2006-04-07

申请人： Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Seong-Geon Pack ,  Taek-Soo Jeon

发明人： Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Seong-Geon Pack ,  Taek-Soo Jeon

IPC分类号： H01L29/74

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a polysilicon layer contacts a gate insulation film while the other transistor includes a gate structure in which a metal layer contacts a gate insulation film.

公开(公告)号：US20060030097A1

公开(公告)日：2006-02-09

申请号：US11183651

申请日：2005-07-18

申请人： Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hong-Bae Park ,  Hag-Ju Cho ,  Hye-Lan Lee ,  Beom-Jun Jin ,  Seong-Geon Park

发明人： Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hong-Bae Park ,  Hag-Ju Cho ,  Hye-Lan Lee ,  Beom-Jun Jin ,  Seong-Geon Park

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842

摘要： A method of forming transistor gate structures in an integrated circuit device can include forming a high-k gate insulating layer on a substrate including a first region to include PMOS transistors and a second region to include NMOS transistors. A polysilicon gate layer can be formed on the high-k gate insulating layer in the first and second regions. A metal silicide gate layer can be formed directly on the high-k gate insulating layer in the first region and avoiding forming the metal-silicide in the second region. Related gate structures are also disclosed.

摘要翻译： 在集成电路器件中形成晶体管栅结构的方法可以包括在包括PMOS晶体管的第一区域的衬底上形成高k栅极绝缘层，以及包括NMOS晶体管的第二区域。 可以在第一和第二区域的高k栅极绝缘层上形成多晶硅栅极层。 可以在第一区域中的高k栅极绝缘层上直接形成金属硅化物栅极层，并且避免在第二区域中形成金属硅化物。 还公开了相关门结构。

公开(公告)号：US07494859B2

公开(公告)日：2009-02-24

申请号：US11400243

申请日：2006-04-10

申请人： Hag-Ju Cho ,  Taek-Soo Jeon ,  Hye-Lan Lee ,  Sang-Bom Kang ,  Yu-Gyun Shin

发明人： Hag-Ju Cho ,  Taek-Soo Jeon ,  Hye-Lan Lee ,  Sang-Bom Kang ,  Yu-Gyun Shin

IPC分类号： H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A semiconductor device comprising a semiconductor substrate having a first impurity region and a second impurity region, a first gate pattern formed on the first impurity region, and a second gate pattern formed on the second impurity region is disclosed. The first gate pattern comprises a first gate insulation layer pattern, a metal layer pattern having a first thickness, and a first polysilicon layer pattern. The second gate pattern comprises a second gate insulation layer pattern, a metal silicide layer pattern having a second thickness smaller than the first thickness, and a second polysilicon layer pattern. The metal silicide layer pattern is formed from a material substantially the same as the material from which the metal layer pattern is formed. A method for manufacturing the semiconductor device is also disclosed.

摘要翻译： 一种半导体器件，包括具有第一杂质区和第二杂质区的半导体衬底，形成在第一杂质区上的第一栅极图案和形成在第二杂质区上的第二栅极图案。 第一栅极图案包括第一栅极绝缘层图案，具有第一厚度的金属层图案和第一多晶硅层图案。 第二栅极图案包括第二栅极绝缘层图案，具有小于第一厚度的第二厚度的金属硅化物层图案和第二多晶硅层图案。 金属硅化物层图案由与形成金属层图案的材料基本相同的材料形成。 还公开了一种半导体器件的制造方法。