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11.发明授权Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device 有权电子器件包括具有与应力层相邻的有源区的晶体管结构和用于形成电子器件的工艺公开(公告)号：US07420202B2
公开(公告)日：2008-09-02
申请号：US11269303
申请日：2005-11-08
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/045 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/7843
摘要： An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.
摘要翻译： 电子器件可以包括第一导电类型的晶体管结构，场隔离区域和覆盖场隔离区域的第一应力类型的层。 例如，晶体管结构可以是p沟道晶体管结构，并且第一应力类型可以是拉伸的，或者晶体管结构可以是n沟道晶体管结构，并且第一应力类型可以是压缩的。 晶体管结构可以包括位于有源区内的沟道区。 有源区域的边缘包括沟道区域和场隔离区域之间的界面。 从顶视图，该层可以包括位于活动区域边缘附近的边缘。 边缘之间的位置关系可以影响晶体管结构的沟道区内的载流子迁移率。
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公开(公告)号：US07214590B2
公开(公告)日：2007-05-08
申请号：US11098874
申请日：2005-04-05
IPC分类号： H01L21/336
CPC分类号： H01L21/823462
摘要： A method of forming an electronic device includes etching a portion of a first gate dielectric layer to reduce a thickness of the gate dielectric layer within that portion. In one embodiment, portions not being etched may be covered by mask. In another embodiment, different portions may be etched during different times to give different thicknesses for the first gate dielectric layer. In a particular embodiment, a second gate dielectric layer may be formed over the first gate dielectric layer after etching the portion. The second gate dielectric layer can have a dielectric constant greater than the dielectric constant of the first gate dielectric layer. Subsequent gate electrode and source/drain region formation can be performed to form a transistor structure.
摘要翻译： 形成电子器件的方法包括蚀刻第一栅极介电层的一部分以减小该部分内的栅极介电层的厚度。 在一个实施例中，未被蚀刻的部分可以被掩模覆盖。 在另一个实施例中，不同部分可以在不同时间被蚀刻，以给予第一栅极介电层不同的厚度。 在特定实施例中，可以在蚀刻该部分之后在第一栅极电介质层上形成第二栅极电介质层。 第二栅极介电层可以具有大于第一栅极介电层的介电常数的介电常数。 可以进行随后的栅电极和源/漏区形成以形成晶体管结构。
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公开(公告)号：US07402472B2
公开(公告)日：2008-07-22
申请号：US11067257
申请日：2005-02-25
IPC分类号： H01L21/336
CPC分类号： H01L21/02329 , H01L21/02181 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/3141 , H01L21/3144 , H01L21/3185 , H01L29/4908 , H01L29/511 , H01L29/6659 , H01L29/7833
摘要： A gate dielectric is treated with a nitridation step and an anneal. After this, an additional nitridation step and anneal is performed. The second nitridation and anneal results in an improvement in the relationship between gate leakage current density and current drive of the transistors that are ultimately formed.
摘要翻译： 用氮化步骤和退火处理栅极电介质。 之后，进行另外的氮化步骤和退火。 第二次氮化和退火导致栅极漏电流密度与最终形成的晶体管的电流驱动之间的关系得到改善。
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公开(公告)号：US07528029B2
公开(公告)日：2009-05-05
申请号：US11408347
申请日：2006-04-21
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for making a semiconductor device. In accordance with the method, a substrate (203) is provided which has first (205) and second (207) gate structures thereon. A first stressor layer (215) is formed over the substrate, and a sacrificial layer (216) is formed over the first stressor layer. A second stressor layer (219) is formed over the sacrificial layer.
摘要翻译： 提供了制造半导体器件的方法。 根据该方法，提供在其上具有第一（205）和第二（207）门结构的衬底（203）。 第一应力层（215）形成在衬底上，牺牲层（216）形成在第一应激层上。 在牺牲层上形成第二应力层（219）。
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公开(公告)号：US06902971B2
公开(公告)日：2005-06-07
申请号：US10624203
申请日：2003-07-21
申请人： Paul A. Grudowski
发明人： Paul A. Grudowski
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L29/78 , H01L21/8238
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/823468 , H01L29/6656 , H01L29/7833 , H01L29/7842
摘要： A semiconductor fabrication process and the resulting integrated circuit include forming a gate electrode (116) over a gate dielectric (104) over a semiconductor substrate (102). A spacer film (124) exhibiting a tensile stress characteristic is deposited over the gate electrode (116). The stress characteristics of at least a portion of the spacer film is then modulated (132, 192) and the spacer film (124) is etched to form sidewall spacers (160, 162) on the gate electrode sidewalls. The spacer film (124) is an LPCVD silicon nitride in one embodiment. Modulating (132) the spacer film (124) includes implanting Xenon or Germanium into the spacers (160) at an implant energy sufficient to break at least some of the silicon nitride bonds. The modulation implant (132) may be performed selectively or non-selectively either before or after etching the spacer film (124).
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16.发明授权Method of preventing two neighboring contacts from a short-circuit caused by a void between them and device having the same 失效防止两个相邻触点之间的空隙引起的短路的装置和具有该触点的装置的方法公开(公告)号：US06369430B1
公开(公告)日：2002-04-09
申请号：US09823310
申请日：2001-04-02
IPC分类号： H01L2976
CPC分类号： H01L21/76831 , H01L21/76802 , H01L21/7682 , H01L21/76897 , H01L21/823425 , H01L21/823475
摘要： Insulating layers between transistors that are very close together may have voids. When contacts are formed in these areas between these close transistors, the contact hole is formed at the void location. These voids may extend between the contact locations that are close together so that the deposition of the conductive material into these contact holes may extend sufficiently into the void to short two such contacts. This is prevented by placing a liner in the contact hole, which constricts the void size in the contact hole, prior to depositing the conductive material. This restricts ingress of conductive material into the void. This prevents the void from being an unwanted conduction path between two contacts that are in close proximity. The bottoms of the contact holes are etched to remove the liner prior to depositing the conductive material.
摘要翻译： 非常靠近在一起的晶体管之间的绝缘层可能具有空隙。 当在这些紧密晶体管之间的这些区域中形成接触时，在空隙位置处形成接触孔。 这些空隙可以在靠近在一起的接触位置之间延伸，使得导电材料沉积到这些接触孔中可以充分地延伸到空隙中以短两个这样的接触。 在沉积导电材料之前，通过将衬垫放置在接触孔中来限制接触孔中的空隙尺寸来防止这种情况。 这限制了导电材料进入空隙。 这样可以防止这两个触点之间的不必要的导电路径的空隙处于非常接近的位置。 在沉积导电材料之前蚀刻接触孔的底部以去除衬垫。
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17.发明授权公开(公告)号：US09847389B2
公开(公告)日：2017-12-19
申请号：US14063459
申请日：2013-10-25
IPC分类号： H01L21/70 , H01L29/06 , H01L21/8234 , H01L21/84 , H01L27/088 , H01L27/12 , H01L29/78
CPC分类号： H01L29/0642 , H01L21/823412 , H01L21/84 , H01L27/088 , H01L27/1203 , H01L29/7842 , H01L29/7843 , H01L29/7846 , H01L29/7849
摘要： An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.
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公开(公告)号：US20110210401A1
公开(公告)日：2011-09-01
申请号：US12713262
申请日：2010-02-26
IPC分类号： H01L27/092 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/0214 , H01L21/0217 , H01L21/02274 , H01L27/092 , H01L29/78 , H01L29/7843
摘要： A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate (209) and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (231) of a first stressor material over the semiconductor structure, said first stressor material containing silicon- nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (233) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.
摘要翻译： 提供一种制造半导体器件的方法，其包括（a）提供配备有栅极（209）和沟道区域的半导体结构，所述沟道区域与栅极相关联; （b）在半导体结构上沉积第一应力源材料的第一子层（231），所述第一应力材料含有硅 - 氮键并向半导体结构施加拉伸应力; （c）通过暴露于辐射源固化第一应激物材料; （d）在所述第一子层上沉积第二应力源材料的第二子层（233），所述第二应力材料含有硅 - 氮键并向所述半导体结构施加拉伸应力; 和（e）通过暴露于辐射源固化应力源材料的第二子层。
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公开(公告)号：US20090142895A1
公开(公告)日：2009-06-04
申请号：US11948209
申请日：2007-11-30
IPC分类号： H01L21/8234
CPC分类号： H01L21/823871 , H01L21/76897 , H01L21/823468 , H01L21/823475 , H01L29/665
摘要： A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an interlayer dielectric layer over the gate electrode, the post-silicide spacer, and the silicide region, and forming a conductive via in the interlayer dielectric layer, extending to the silicide region.
摘要翻译： 形成通孔的方法包括在半导体衬底上形成栅电极，在与栅电极相邻的半导体衬底中形成源极/漏极区域，在源/漏区域中形成硅化物区域，形成邻近硅化物间隔区 在形成硅化物区域之后形成栅电极，在栅电极，硅化物间隔物和硅化物区域之上形成层间电介质层，并且在层间电介质层中形成延伸到硅化物区域的导电通孔。
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公开(公告)号：US20080293192A1
公开(公告)日：2008-11-27
申请号：US11751724
申请日：2007-05-22
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L21/26506 , H01L29/665 , H01L29/66628 , H01L29/66772 , H01L29/7843
摘要： A semiconductor device is formed in a semiconductor layer. A gate dielectric is formed over a top surface of the semiconductor layer. A gate stack is over the gate dielectric. A sidewall spacer is formed around the gate stack. Using the sidewall spacer as a mask, an implant is performed to form deep source/drain regions in the semiconductor layer. Silicon carbon regions are formed on the deep source/drain regions and a top surface of the gate stack. The silicon carbon regions are silicided with nickel.
摘要翻译： 在半导体层中形成半导体器件。 在半导体层的顶表面上形成栅极电介质。 栅极堆叠在栅极电介质上方。 在栅堆叠周围形成侧壁间隔物。 使用侧壁间隔件作为掩模，进行注入以在半导体层中形成深的源极/漏极区域。 在深源极/漏极区域和栅极堆叠的顶表面上形成硅碳区域。 硅碳区域用镍硅化。
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