公开(公告)号：US20060199379A1

公开(公告)日：2006-09-07

申请号：US11071104

申请日：2005-03-04

申请人： Ming-Shih Yeh ,  Ming-Hsing Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Ming-Shih Yeh ,  Ming-Hsing Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L21/4763 ,  H01L21/31

CPC分类号： H01L21/76804 ,  H01L21/31144 ,  H01L21/314 ,  H01L21/76808 ,  Y10S438/978

摘要： The manufacture of damascene structures having improved performance, particularly, but not by way of limitation, dual damascene structures is provided. In one embodiment, a substrate having a conductive layer is formed in a first insulating layer. A protective layer is formed above the conductive layer. An etching stop layer is formed above the protective layer and the first insulating layer. A second insulating layer is formed above the etching stop layer. A first patterned photoresist layer is formed above the second insulating layer, the first patterned photoresist layer having a first pattern. The first pattern is etched into the second insulating layer and the etching stop layer to form a first opening. A via plug is filled at least partially in the first opening. An anti-reflective coating (ARC) layer is formed above the second insulating layer. A second patterned photoresist layer is formed above the ARC layer, the second photoresist layer having a second pattern. The second pattern is etched into portions of the via plug, second insulation layer, and the ARC layer to form a second opening, wherein a substantially tapered sidewall portion is formed at the interface of the first and second openings.

摘要翻译： 提供了具有改进的性能，特别但非限制性的双镶嵌结构的镶嵌结构的制造。 在一个实施例中，具有导电层的衬底形成在第一绝缘层中。 在导电层上形成保护层。 在保护层和第一绝缘层上方形成蚀刻停止层。 在蚀刻停止层上形成第二绝缘层。 第一图案化光致抗蚀剂层形成在第二绝缘层之上，第一图案化光致抗蚀剂层具有第一图案。 将第一图案蚀刻到第二绝缘层和蚀刻停止层中以形成第一开口。 通孔插塞至少部分地填充在第一开口中。 在第二绝缘层上方形成抗反射涂层（ARC）层。 第二图案化光致抗蚀剂层形成在ARC层上方，第二光致抗蚀剂层具有第二图案。 第二图案被蚀刻到通孔塞，第二绝缘层和ARC层的部分中以形成第二开口，其中在第一和第二开口的界面处形成大致锥形的侧壁部分。

公开(公告)号：US20050245072A1

公开(公告)日：2005-11-03

申请号：US10833154

申请日：2004-04-28

申请人： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

发明人： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

IPC分类号： H01L21/288 ,  H01L21/4763 ,  H01L21/76 ,  H01L21/768

CPC分类号： H01L21/2885 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76873 ,  H01L21/76877

摘要： A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle θ less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.

摘要翻译： 电化学沉积（ECD）的方法在衬底上提供阻挡层和种子层。 在将金属层电化学沉积在具有物理或化学表面处理工艺的电化学镀覆电池中之前，对基板的表面进行预处理。 电化学镀覆电池被盖覆盖以防止电解质溶液的蒸发。 电化学电镀单元包括具有提升密封件的衬底保持器组件，例如在提升密封件和衬底之间的接触角θ小于90°。 衬底保持器组件包括在衬底的后侧的衬底卡盘。

公开(公告)号：US20050097769A1

公开(公告)日：2005-05-12

申请号：US10668291

申请日：2003-09-24

申请人： Jing-Cheng Lin ,  Shing-Chyang Pan ,  Hsien-Ming Lee ,  Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai ,  Shau-Lin Shue

发明人： Jing-Cheng Lin ,  Shing-Chyang Pan ,  Hsien-Ming Lee ,  Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai ,  Shau-Lin Shue

IPC分类号： H01L21/677 ,  F26B13/30

CPC分类号： H01L21/67781

摘要： A loadlock. The loadlock for wafers includes a chamber, a pedestal, a retractable shaft, and a bellows. The chamber has a plurality of walls and a bottom surface. The pedestal supports a cassette and is disposed in the chamber. The retractable shaft has a top end and a bottom end. The top end is connected to the pedestal and the bottom end is connected to the bottom surface as a reference for positioning the pedestal. The bellows has a first end and a second end. The first end is disposed on the pedestal and the second end is sealed at the bottom end of the retractable shaft. Preferably, the retractable shaft is fully enclosed by the bellows.

摘要翻译： 一个加载锁 用于晶片的负荷锁包括一个腔室，一个基座，一个伸缩轴和一个波纹管。 腔室具有多个壁和底面。 基座支撑盒并设置在腔室中。 伸缩轴具有顶端和底端。 顶端连接到基座，底端连接到底面作为基座的基准。 波纹管具有第一端和第二端。 第一端设置在基座上，第二端在可伸缩轴的底端被密封。 优选地，可伸缩轴被波纹管完全包围。

公开(公告)号：US06878615B2

公开(公告)日：2005-04-12

申请号：US09863224

申请日：2001-05-24

申请人： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L2221/1063

摘要： A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.

摘要翻译： 公开了一种在低k电介质材料中形成通孔并且不伴随通过中毒问题的方法，或者形成在相同电介质中并且没有相同问题的双镶嵌结构。 通孔开口的垂直壁首先衬有低k保护层，然后被阻挡层覆盖，以便当铜沉积到通孔中时，防止从低k电介质材料脱气。 在双镶嵌结构的情况下，沟槽开口下方的开孔首先衬有低k保护层就足够了。 所得到的通孔或双镶嵌结构没有中毒金属，因此更可靠。

公开(公告)号：US20050054196A1

公开(公告)日：2005-03-10

申请号：US10657505

申请日：2003-09-08

申请人： Chii-Ming Wu ,  Ming-Hsing Tsai ,  Ching-Hua Hsieh ,  Shau-Lin Shue

发明人： Chii-Ming Wu ,  Ming-Hsing Tsai ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/8249

CPC分类号： H01L21/76877 ,  H01L21/28562 ,  H01L23/53261 ,  H01L2924/0002 ,  H01L2924/00

摘要： An atomic layer deposition method is used to deposit a TiN or TiSiN film having a thickness of about 50 nm or less on a substrate. A titanium precursor which is tetrakis(dimethylamido)titanium (TDMAT), tetrakis(diethylamido)titanium (TDEAT), or Ti{OCH(CH3)2}4 avoids halide contamination from a titanium halide precursor and is safer to handle than a titanium nitrate. After a monolayer of the titanium precursor is deposited on a substrate, a nitrogen containing reactant is introduced to form a TiN monolayer which is followed by a second purge. For TiSiN, a silicon source gas is fed into the process chamber after the TiN monolayer formation. The process is repeated several times to produce a composite layer comprised of a plurality of monolayers that fills a contact hole. The ALD method is cost effective and affords an interconnect with lower impurity levels and better step coverage than conventional PECVD or CVD processes.

摘要翻译： 使用原子层沉积方法在衬底上沉积厚度约为50nm或更小的TiN或TiSiN膜。 四（二甲基氨基）钛（TDMAT），四（二乙基酰氨基）钛（TDEAT）或Ti {OCH（CH 3）2} 4）的钛前体避免了卤化钛前体的卤化物污染，并且比硝酸钛更安全 。 将钛前体的单层沉积在基底上之后，引入含氮反应物以形成TiN单层，随后进行第二次吹扫。 对于TiSiN，在TiN单层形成之后，将硅源气体进料到处理室中。 该过程重复几次以产生由填充接触孔的多个单层组成的复合层。 ALD方法具有成本效益，并且提供了比常规PECVD或CVD工艺更低的杂质水平和更好的阶梯覆盖的互连。

公开(公告)号：US6140241A

公开(公告)日：2000-10-31

申请号：US270591

申请日：1999-03-18

申请人： Shau-Lin Shue ,  Ming-Hsing Tsai ,  Wen-Jye Tsai ,  Chen-Hua Yu

发明人： Shau-Lin Shue ,  Ming-Hsing Tsai ,  Wen-Jye Tsai ,  Chen-Hua Yu

IPC分类号： H01L21/288 ,  H01L21/768 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76877 ,  H01L21/2885

摘要： A multi-step electrochemical method for forming a copper metallurgy on an integrated circuit which has high aspect ratio contact/via openings is described. The method is designed to give good coverage and gap filling capability as well as high production throughput by performing the electrochemical deposition of copper in two deposition stages with an dwell period between the stages. The process utilizes a copper plating electrolyte which contains an added brightener and leveler. The first deposition is done at a low current density which provides good coverage resulting from a high throwing power. The high aspect ratio contact/via openings are covered with a substantial thickness of a uniform, high quality copper coating. During the deposition, the concentration of brightener becomes depleted in the base region of high aspect ratio contacts or vias. The concentration of brighteners, is replenished in these regions by diffusion during a brief dwell period wherein the plating current is stopped. Next, a high current density is applied whereby the contact/vias are filled and additional copper is deposited over them at a high deposition rate. The greatest throughput benefits are realized, by way of the high current density step, when the process is applied to the formation of a dual damascene metallurgy.

摘要翻译： 描述了在具有高纵横比接触/通孔开口的集成电路上形成铜冶金的多步电化学方法。 该方法设计为通过在两个沉积阶段之间执行铜的电化学沉积，具有阶段之间的停留时间，以提供良好的覆盖和间隙填充能力以及高的生产量。 该方法使用含有添加的增白剂和矫直机的镀铜电解质。 第一次沉积以低电流密度进行，这提供了由高投掷功率引起的良好覆盖。 高长宽比的接触/通孔开口用相当厚度的均匀的高质量铜涂层覆盖。 在沉积期间，增亮剂的浓度在高纵横比触点或通孔的基极区域中耗尽。 增亮剂的浓度，在电镀电流停止的短暂停留期间通过扩散在这些区域补充。 接下来，施加高电流密度，由此接触/通孔被填充，并且以高沉积速率在其上沉积额外的铜。 通过高电流密度步骤，当该方法应用于双镶嵌冶金的形成时，实现了最大的生产效率。

公开(公告)号：US07354856B2

公开(公告)日：2008-04-08

申请号：US11071104

申请日：2005-03-04

申请人： Ming-Shih Yeh ,  Ming-Hsing Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Ming-Shih Yeh ,  Ming-Hsing Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L21/44

CPC分类号： H01L21/76804 ,  H01L21/31144 ,  H01L21/314 ,  H01L21/76808 ,  Y10S438/978

摘要： The manufacture of damascene structures having improved performance, particularly, but not by way of limitation, dual damascene structures is provided. In one embodiment, a substrate having a conductive layer is formed in a first insulating layer. A protective layer is formed above the conductive layer. An etching stop layer is formed above the protective layer and the first insulating layer. A second insulating layer is formed above the etching stop layer. A first patterned photoresist layer is formed above the second insulating layer, the first patterned photoresist layer having a first pattern. The first pattern is etched into the second insulating layer and the etching stop layer to form a first opening. A via plug is filled at least partially in the first opening. An anti-reflective coating (ARC) layer is formed above the second insulating layer. A second patterned photoresist layer is formed above the ARC layer, the second photoresist layer having a second pattern. The second pattern is etched into portions of the via plug, second insulation layer, and the ARC layer to form a second opening, wherein a substantially tapered sidewall portion is formed at the interface of the first and second openings.

摘要翻译： 提供了具有改进的性能，特别但非限制性的双镶嵌结构的镶嵌结构的制造。 在一个实施例中，具有导电层的衬底形成在第一绝缘层中。 在导电层上形成保护层。 在保护层和第一绝缘层上方形成蚀刻停止层。 在蚀刻停止层上形成第二绝缘层。 第一图案化光致抗蚀剂层形成在第二绝缘层之上，第一图案化光致抗蚀剂层具有第一图案。 将第一图案蚀刻到第二绝缘层和蚀刻停止层中以形成第一开口。 通孔塞至少部分地填充在第一开口中。 在第二绝缘层上方形成抗反射涂层（ARC）层。 第二图案化光致抗蚀剂层形成在ARC层上方，第二光致抗蚀剂层具有第二图案。 第二图案被蚀刻到通孔塞，第二绝缘层和ARC层的部分中以形成第二开口，其中在第一和第二开口的界面处形成大致锥形的侧壁部分。

公开(公告)号：US20070287294A1

公开(公告)日：2007-12-13

申请号：US11448713

申请日：2006-06-08

申请人： Ting-Chu Ko ,  Ming-Hsing Tsai ,  Shau-Lin Shue

发明人： Ting-Chu Ko ,  Ming-Hsing Tsai ,  Shau-Lin Shue

IPC分类号： H01L21/302 ,  H01L21/31

CPC分类号： H01L21/3105 ,  H01L21/321 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76859

摘要： Methods for fabricating interconnect structures are provided. An exemplary method for fabricating an interconnect comprises providing a substrate with a first dielectric layer thereon. At least one conductive feature is formed in the first dielectric layer. A conductive cap is selectively formed to overlie the conductive feature. A surface treatment is performed on the first dielectric layer and the conductive cap. A second dielectric layer is then formed to overlie the first dielectric layer.

摘要翻译： 提供制造互连结构的方法。 用于制造互连的示例性方法包括在其上提供其上具有第一介电层的衬底。 在第一介电层中形成至少一个导电特征。 选择性地形成导电盖以覆盖导电特征。 在第一电介质层和导电盖上进行表面处理。 然后形成第二电介质层以覆盖第一电介质层。

公开(公告)号：US07250683B2

公开(公告)日：2007-07-31

申请号：US11056758

申请日：2005-02-11

申请人： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L2221/1063

摘要： A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.

摘要翻译： 公开了一种在低k电介质材料中形成通孔并且不伴随通过中毒问题的方法，或者形成在相同电介质中并且没有相同问题的双镶嵌结构。 通孔开口的垂直壁首先衬有低k保护层，然后被阻挡层覆盖，以便当铜沉积到通孔中时，防止从低k电介质材料脱气。 在双镶嵌结构的情况下，沟槽开口下方的开孔首先衬有低k保护层就足够了。 所得到的通孔或双镶嵌结构没有中毒金属，因此更可靠。

公开(公告)号：US07226860B2

公开(公告)日：2007-06-05

申请号：US10833154

申请日：2004-04-28

申请人： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

发明人： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

IPC分类号： H01L21/44

CPC分类号： H01L21/2885 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76873 ,  H01L21/76877

摘要： A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle θ less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.