公开(公告)号：US20120021602A1

公开(公告)日：2012-01-26

申请号：US13249823

申请日：2011-09-30

Applicant: Ting-Chu Ko ,  Ming-Hsing Tsai ,  Chien-Hsueh Shih

Inventor： Ting-Chu Ko ,  Ming-Hsing Tsai ,  Chien-Hsueh Shih

IPC: H01L21/768

CPC classification number: H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.

Abstract translation: 提供了一种方法和系统，用于有效地改变半导体器件的金属互连的组成。 根据本公开的金属互连在电介质材料上具有中间层，中间层与主金属一起具有较高浓度的杂质金属，杂质金属具有比初级金属低的还原电位。 金属互连件在中间层的顶部具有金属合金互连的主层，被中间层包围，主层具有比中间层更高的一次金属浓度，其中，中间层和中间层的中间层和主要层 金属合金互连件均保持材料均匀性。

公开(公告)号：US20060118422A1

公开(公告)日：2006-06-08

申请号：US11004294

申请日：2004-12-03

Applicant: Ting-Chu Ko ,  Chien-Hsueh Shih ,  Minghsing Tsai

Inventor： Ting-Chu Ko ,  Chien-Hsueh Shih ,  Minghsing Tsai

IPC: C25D5/00 ,  H01L21/44

CPC classification number: C25D3/38 ,  C25D3/02 ,  H01L21/2885 ,  H01L21/76877

Abstract: A chemical solution for an electro chemical plating process includes an electro chemical plating solution; and an additive, added in the electro chemical plating solution, substantially consisting of a polymer with one or more kinds of impurities, wherein each kind of the impurities has a density, with respect to the polymer, lower then 1019 atoms/cc.

Abstract translation: 化学电镀工艺的化学溶液包括电化学镀液; 以及添加在电化学镀液中的添加剂，其基本上由具有一种或多种杂质的聚合物组成，其中各种杂质相对于聚合物的密度低于1019原子/ cc。

公开(公告)号：US07026244B2

公开(公告)日：2006-04-11

申请号：US10637105

申请日：2003-08-08

Applicant: Ting-Chu Ko ,  Ming-Hsing Tsai ,  Chien-Hsueh Shih

Inventor： Ting-Chu Ko ,  Ming-Hsing Tsai ,  Chien-Hsueh Shih

IPC: H01C23/48

CPC classification number: H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.

Abstract translation: 提供了一种方法和系统，用于有效地改变半导体器件的金属互连的组成。 根据本公开的金属互连在电介质材料上具有中间层，中间层与主金属一起具有较高浓度的杂质金属，杂质金属具有比初级金属低的还原电位。 金属互连件在中间层的顶部具有金属合金互连的主层，被中间层包围，主层具有比中间层更高的一次金属浓度，其中，中间层和中间层的中间层和主要层 金属合金互连件均保持材料均匀性。

公开(公告)号：US20140048888A1

公开(公告)日：2014-02-20

申请号：US13588860

申请日：2012-08-17

Applicant: Chung-Hsien Chen ,  Ting-Chu Ko ,  Chih-Hao Chang ,  Chih-Sheng Chang ,  Shou-Zen Chang ,  Clement Hsingjen Wann

Inventor： Chung-Hsien Chen ,  Ting-Chu Ko ,  Chih-Hao Chang ,  Chih-Sheng Chang ,  Shou-Zen Chang ,  Clement Hsingjen Wann

IPC: H01L27/092 ,  H01L21/20

CPC classification number: H01L21/02664 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7845 ,  H01L29/7848

Abstract: A semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and a P-silicide region on the P-strained region; and an n-type Field Effect Transistor (nFET) comprising: an N-gate stack over the major surface, an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and a N-silicide region on the N-strained region.

公开(公告)号：US08053892B2

公开(公告)日：2011-11-08

申请号：US11341827

申请日：2006-01-27

Applicant: Ting-Chu Ko ,  Ming-Hsing Tsai ,  Chien-Hsueh Shih

Inventor： Ting-Chu Ko ,  Ming-Hsing Tsai ,  Chien-Hsueh Shih

IPC: H01L23/48

CPC classification number: H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.

Abstract translation: 提供了一种方法和系统，用于有效地改变半导体器件的金属互连的组成。 根据本公开的金属互连在电介质材料上具有中间层，中间层与主金属一起具有较高浓度的杂质金属，杂质金属具有比初级金属低的还原电位。 金属互连件在中间层的顶部具有金属合金互连的主层，被中间层包围，主层具有比中间层更高的一次金属浓度，其中，中间层和中间层的中间层和主要层 金属合金互连件均保持材料均匀性。

公开(公告)号：US20050045485A1

公开(公告)日：2005-03-03

申请号：US10654523

申请日：2003-09-03

Applicant: Chien-Hsueh Shih ,  Ting-Chu Ko ,  Minghsing Tsai

Inventor： Chien-Hsueh Shih ,  Ting-Chu Ko ,  Minghsing Tsai

IPC: C25D3/38 ,  C25D5/10 ,  C25D7/12 ,  C25D15/00 ,  H01L21/288 ,  H01L21/768 ,  H05K3/42 ,  C25D5/02 ,  H01L21/445

CPC classification number: H01L21/76877 ,  C25D3/38 ,  C25D5/10 ,  C25D7/123 ,  C25D15/00 ,  H01L21/2885 ,  H05K3/423

Abstract: A method for reducing or avoiding copper layer pitting in a copper electrochemical deposition process to improve deposition uniformity including providing a substrate for carrying out at least a first copper electroplating process; providing a copper electroplating solution including a deforming (antiforming) agent wherein the antiforming (deforming) agent includes at least one alkylene monomer; and, carrying out at least a first copper electroplating process to deposit at least a first copper layer.

Abstract translation: 一种用于在铜电化学沉积工艺中减少或避免铜层点蚀以改善沉积均匀性的方法，包括提供用于执行至少第一铜电镀工艺的衬底; 提供包括变形（防形）剂的铜电镀溶液，其中抗变形（变形）试剂包括至少一种亚烷基单体; 并且进行至少第一铜电镀工艺以至少沉积第一铜层。

公开(公告)号：US08785321B2

公开(公告)日：2014-07-22

申请号：US13249823

申请日：2011-09-30

Applicant: Ting-Chu Ko ,  Ming-Hsing Tsai ,  Chien-Hsueh Shih

Inventor： Ting-Chu Ko ,  Ming-Hsing Tsai ,  Chien-Hsueh Shih

IPC: H01L21/4763

CPC classification number: H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.

Abstract translation: 提供了一种方法和系统，用于有效地改变半导体器件的金属互连的组成。 根据本公开的金属互连在电介质材料上具有中间层，中间层与主金属一起具有较高浓度的杂质金属，杂质金属具有比初级金属低的还原电位。 金属互连件在中间层的顶部具有金属合金互连的主层，被中间层包围，主层具有比中间层更高的一次金属浓度，其中，中间层和中间层的中间层和主要层 金属合金互连件均保持材料均匀性。

公开(公告)号：US08716863B2

公开(公告)日：2014-05-06

申请号：US13182368

申请日：2011-07-13

Applicant: Hsingjen Wann ,  Ting-Chu Ko

Inventor： Hsingjen Wann ,  Ting-Chu Ko

IPC: H01L23/48 ,  H01L29/40 ,  H01L23/52 ,  H01L21/02

CPC classification number: H01L21/76843 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides an integrated circuit structure. The integrated circuit structure includes a substrate having an IC device formed therein; a first dielectric material layer disposed on the substrate and having a first trench formed therein; and a first composite interconnect feature disposed in the first trench and electrically coupled with the IC device. The first composite interconnect feature includes a first barrier layer disposed on sidewalls of the first trench; a first metal layer disposed on the first barrier layer; and a first graphene layer disposed on the metal layer.

Abstract translation: 本发明提供一种集成电路结构。 集成电路结构包括其中形成有IC器件的衬底; 第一电介质材料层，设置在所述衬底上并且具有形成在其中的第一沟槽; 以及设置在所述第一沟槽中并与所述IC器件电耦合的第一复合互连特征。 第一复合互连特征包括设置在第一沟槽的侧壁上的第一阻挡层; 设置在所述第一阻挡层上的第一金属层; 以及设置在所述金属层上的第一石墨烯层。

公开(公告)号：US20070054488A1

公开(公告)日：2007-03-08

申请号：US11341827

申请日：2006-01-27

Applicant: Ting-Chu Ko ,  Ming-Hsing Tsai ,  Chien-Hsueh Shih

Inventor： Ting-Chu Ko ,  Ming-Hsing Tsai ,  Chien-Hsueh Shih

IPC: H01L21/4763

CPC classification number: H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.

Abstract translation: 提供了一种方法和系统，用于有效地改变半导体器件的金属互连的组成。 根据本公开的金属互连在电介质材料上具有中间层，中间层与主金属一起具有较高浓度的杂质金属，杂质金属具有比初级金属低的还原电位。 金属互连件在中间层的顶部具有金属合金互连的主层，被中间层包围，主层具有比中间层更高的一次金属浓度，其中，中间层和中间层的中间层和主要层 金属合金互连件均保持材料均匀性。

公开(公告)号：US20130015581A1

公开(公告)日：2013-01-17

申请号：US13182368

申请日：2011-07-13

Applicant: Hsingjen Wann ,  Ting-Chu Ko

Inventor： Hsingjen Wann ,  Ting-Chu Ko

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides an integrated circuit structure. The integrated circuit structure includes a substrate having an IC device formed therein; a first dielectric material layer disposed on the substrate and having a first trench formed therein; and a first composite interconnect feature disposed in the first trench and electrically coupled with the IC device. The first composite interconnect feature includes a first barrier layer disposed on sidewalls of the first trench; a first metal layer disposed on the first barrier layer; and a first graphene layer disposed on the metal layer.

Abstract translation: 本发明提供一种集成电路结构。 集成电路结构包括其中形成有IC器件的衬底; 第一电介质材料层，设置在所述衬底上并且具有形成在其中的第一沟槽; 以及设置在所述第一沟槽中并与所述IC器件电耦合的第一复合互连特征。 第一复合互连特征包括设置在第一沟槽的侧壁上的第一阻挡层; 设置在所述第一阻挡层上的第一金属层; 以及设置在所述金属层上的第一石墨烯层。