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公开(公告)号：US20140097542A1
公开(公告)日：2014-04-10
申请号：US13975485
申请日：2013-08-26
发明人： Xiaochun Tan
IPC分类号： H01L23/498
CPC分类号： H01L23/49811 , H01L23/49816 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/13082 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/1601 , H01L2224/16238 , H01L2224/81193 , H01L2224/81205 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2924/3511 , H01L2924/00014
摘要： Disclosed is a flip chip packaging device and structure of interconnections between a chip and a substrate. In one embodiment, a flip chip packaging device can include: (i) a chip and a substrate; (ii) a plurality of first connecting structures and a plurality of second connecting structures that are aligned and configured to electrically connect the chip and the substrate; and (iii) where each of the plurality of first connecting structures comprises a first metal, and each of the plurality of second connecting structures comprises a second metal, and where a hardness of the first metal is less than a hardness of the second metal.
摘要翻译： 公开了一种倒装芯片封装器件和芯片与衬底之间的互连结构。 在一个实施例中，倒装芯片封装器件可以包括：（i）芯片和衬底; （ii）多个第一连接结构和多个第二连接结构，其被对准和配置成电连接芯片和基板; 和（iii）其中多个第一连接结构中的每一个包括第一金属，并且多个第二连接结构中的每一个包括第二金属，并且其中第一金属的硬度小于第二金属的硬度。
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公开(公告)号：US11462510B2
公开(公告)日：2022-10-04
申请号：US16913096
申请日：2020-06-26
发明人： Xiaochun Tan
摘要： A stacked package structure for a chip, can include: a substrate having a first surface and a second surface opposite thereto; a first die having an active and back faces, where the active face of the first die includes pads; a first enclosure that covers the first die; an interlinkage that extends to the first enclosure to electrically couple with the pads; a first redistribution body electrically coupled to the interlinkage, and being partially exposed on a surface of the stacked package structure to provide outer pins for electrically coupling to external circuitry; a penetrating body that penetrates the first enclosure and substrate; a second die having an electrode electrically coupled to a first terminal of the penetrating body; and a second terminal of the penetrating body that is exposed on the surface of the stacked package structure to provide outer pins for electrically coupling to the external circuitry.
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公开(公告)号：US20200328191A1
公开(公告)日：2020-10-15
申请号：US16913096
申请日：2020-06-26
发明人： Xiaochun Tan
IPC分类号： H01L25/065 , H01L23/31 , H01L25/00 , H01L25/03 , H01L23/00
摘要： A stacked package structure for a chip, can include: a substrate having a first surface and a second surface opposite thereto; a first die having an active and back faces, where the active face of the first die includes pads; a first enclosure that covers the first die; an interlinkage that extends to the first enclosure to electrically couple with the pads; a first redistribution body electrically coupled to the interlinkage, and being partially exposed on a surface of the stacked package structure to provide outer pins for electrically coupling to external circuitry; a penetrating body that penetrates the first enclosure and substrate; a second die having an electrode electrically coupled to a first terminal of the penetrating body; and a second terminal of the penetrating body that is exposed on the surface of the stacked package structure to provide outer pins for electrically coupling to the external circuitry.
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14.发明授权公开(公告)号：US10128221B2
公开(公告)日：2018-11-13
申请号：US14598679
申请日：2015-01-16
发明人： Xiaochun Tan , Jiaming Ye
IPC分类号： H01L23/48 , H01L23/52 , H01L23/02 , H01L23/34 , H01L25/16 , H01L25/00 , H01L23/495 , H01L21/48 , H01L23/00 , H01L23/498 , H01L23/31
摘要： A package assembly and a method for manufacturing the same are disclosed. The package assembly includes a leadframe having at least two groups of leads and a plurality of electronic devices arranged in at least two levels. Each group of leads is electrically coupled to a respective level of electronic devices. The package assembly further includes an interconnect for coupling one or more leads of one group of leads to one or more leads of another group of leads. The package assembly results in increased packaging density, less usage of bonding wires in the package assembly, improves reliability, and prevents possible interference.
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公开(公告)号：US10043738B2
公开(公告)日：2018-08-07
申请号：US14601098
申请日：2015-01-20
发明人： Jiaming Ye , Xiaochun Tan
IPC分类号： H01L23/495 , H01L23/00
摘要： In one embodiment, an IC package assembly for a switching regulator, can include: a power switch chip including a control electrode and a first electrode on an obverse side and a second electrode on a reverse side, where the second electrode is configured as a switching terminal of a switching regulator; a control chip including a driving electrode and a plurality of input and output electrodes on the obverse side; and a leadframe including an extension pin, a substrate, and a plurality of discrete pins, where the extension pin is formed integrally with the substrate, and where the reverse side of the power switch chip is arranged on the substrate of the leadframe by a conductive material to electrically connect the second electrode to the substrate.
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公开(公告)号：US09373567B2
公开(公告)日：2016-06-21
申请号：US14459515
申请日：2014-08-14
发明人： Xiaochun Tan
IPC分类号： H01L23/495
CPC分类号： H01L23/4952 , H01L23/495 , H01L23/49513 , H01L23/49575 , H01L2224/16245 , H01L2224/32145 , H01L2224/32245 , H01L2224/48247 , H01L2224/73265 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： Disclosed herein are various chip lead frame and packaging structures, and methods of fabrication. In one embodiment, a lead frame can include: (i) a horizontal plate arranged at a bottom of the lead frame, where the horizontal plate is conductive; and (ii) a plurality of conductive bumps arranged on a surface of the horizontal plate, where the plurality of conductive bumps are configured to support and electrically connect to at least one chip. In one embodiment, a method of making the lead frame can include: (i) forming the horizontal plate by a mold; (ii) arranging a mask with a through-hole on the surface of the horizontal plate; (iii) electroplating conducting material on a portion of the horizontal plate that is exposed by the through-hole; and (iv) removing the mask after formation of the plurality of conductive bumps. Also, a package structure can be formed using the lead frame.
摘要翻译： 本文公开了各种芯片引线框架和封装结构以及制造方法。 在一个实施例中，引线框架可以包括：（i）布置在引线框架的底部的水平板，其中水平板是导电的; 以及（ii）布置在所述水平板的表面上的多个导电凸块，其中所述多个导电凸块构造成支撑并电连接至少一个芯片。 在一个实施例中，制造引线框架的方法可以包括：（i）通过模具形成水平板; （ii）在水平板的表面上布置具有通孔的掩模; （iii）在由通孔露出的水平板的一部分上的电镀导电材料; 和（iv）在形成多个导电凸块之后去除掩模。 此外，可以使用引线框形成封装结构。
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公开(公告)号：US09054088B2
公开(公告)日：2015-06-09
申请号：US14077425
申请日：2013-11-12
发明人： Xiaochun Tan
IPC分类号： H01L23/498 , H01L23/495 , H01L23/64 , H01L25/16 , H01L23/00
CPC分类号： H01L23/495 , H01L23/645 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L25/16 , H01L2224/131 , H01L2224/16225 , H01L2224/16245 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2924/12041 , H01L2924/19042 , H01L2924/19104 , H01L2924/19107 , H01L2924/30107 , H01L2924/00014 , H01L2924/014 , H01L2924/00 , H01L2924/00012
摘要： Disclosed herein are various chip packaging structures and arrangements. In one embodiment, a multiple-component chip packaging structure can include: (i) a first component arranged on a bottom layer; (ii) at least one second component arranged on the first component, where the at least one the second component is electrically connected to the first component by a plurality of protruding structures; (iii) at least one third component on the at least one second component; (iv) at least one extension structure arranged on at least one side of the at least one third component, where the at least one extension structure is configured to lead out electric polarities of the at least one third component; and (v) a plurality of bonding wires that electrically connect the at least one extension structure to the first component.
摘要翻译： 本文公开了各种芯片封装结构和布置。 在一个实施例中，多部件芯片封装结构可以包括：（i）布置在底层上的第一部件; （ii）布置在第一部件上的至少一个第二部件，其中所述第二部件中的至少一个通过多个突出结构电连接到第一部件; （iii）至少一个第二组分上的至少一种第三组分; （iv）布置在所述至少一个第三部件的至少一侧上的至少一个延伸结构，其中所述至少一个延伸结构被配置为引出所述至少一个第三部件的电极性; 和（v）将所述至少一个延伸结构电连接到所述第一部件的多个接合线。
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公开(公告)号：US20140070390A1
公开(公告)日：2014-03-13
申请号：US13973132
申请日：2013-08-22
发明人： Xiaochun Tan , Wei Chen
IPC分类号： H01L23/495 , H01L23/00
CPC分类号： H01L23/495 , H01L23/3107 , H01L23/49575 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/80 , H01L24/92 , H01L2224/04042 , H01L2224/05554 , H01L2224/29006 , H01L2224/2919 , H01L2224/32135 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48145 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Disclosed are multi-chip packaging structures and methods. In one embodiment, a multi-chip packaging structure can include: (i) N chips, where N is an integer of at least two, and where an upper surface of each chip comprises a plurality of pads; (ii) a lead frame with a chip carrier and a plurality of pins, where the N chips are stacked in layers on the chip carrier, and where a chip in an upper layer partially covers a chip in a lower layer such that the plurality of pads of the lower layer chip are exposed; (iii) a plurality of first bonding leads configured to connect pads on one chip to pads on another chip; and (iv) a plurality of second bonding leads configured to connect pads on at least one chip to the plurality of pins for external connection to the multi-chip packaging structure.
摘要翻译： 公开了多芯片封装结构和方法。 在一个实施例中，多芯片封装结构可以包括：（i）N个芯片，其中N是至少为2的整数，并且其中每个芯片的上表面包括多个焊盘; （ii）具有芯片载体和多个引脚的引线框架，其中N个芯片层叠在芯片载体上，并且其中上层中的芯片部分地覆盖下层中的芯片，使得多个 下层芯片的焊盘露出; （iii）多个第一接合引线，其被配置为将一个芯片上的焊盘连接到另一个芯片上的焊盘; 以及（iv）多个第二接合引线，其被配置为将至少一个芯片上的焊盘连接到所述多个引脚以用于与所述多芯片封装结构的外部连接。
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公开(公告)号：US10763241B2
公开(公告)日：2020-09-01
申请号：US15283573
申请日：2016-10-03
发明人： Xiaochun Tan
摘要： A stacked package structure for a chip, can include: a substrate having a first surface and a second surface opposite thereto; a first die having an active and back faces, where the active face of the first die includes pads; a first enclosure that covers the first die; an interlinkage that extends to the first enclosure to electrically couple with the pads; a first redistribution body electrically coupled to the interlinkage, and being partially exposed on a surface of the stacked package structure to provide outer pins for electrically coupling to external circuitry; a penetrating body that penetrates the first enclosure and substrate; a second die having an electrode electrically coupled to a first terminal of the penetrating body; and a second terminal of the penetrating body that is exposed on the surface of the stacked package structure to provide outer pins for electrically coupling to the external circuitry.
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公开(公告)号：US20190198351A1
公开(公告)日：2019-06-27
申请号：US16291108
申请日：2019-03-04
发明人： Xiaochun Tan
IPC分类号： H01L21/56 , H01L23/367 , H01L23/498 , H01L23/538 , H01L23/31 , H01L23/00
CPC分类号： H01L21/56 , H01L23/3121 , H01L23/3677 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/92 , H01L2224/04105 , H01L2224/24226 , H01L2224/32225 , H01L2224/73267 , H01L2224/82031 , H01L2224/82039 , H01L2224/92244 , H01L2924/19042 , H01L2924/19043
摘要： A package structure can include: (i) a substrate having opposite first and second surfaces; (ii) a die having opposite active and back surfaces, where the die is arranged above the first surface of the substrate, the back surface of the die is adjacent to the first surface of the substrate; (iii) pads arranged on the active surface of the die; (iv) a first encapsulator configured to encapsulate the die; (v) an interconnection structure configured to electrically connect to the pads through the first encapsulator; (vi) a second encapsulator configured to encapsulate the interconnection structure; and (vii) a redistribution structure configured to electrically connect to the interconnection structure and to provide external electrical connectivity.
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