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    VERIFICATION METHOD AND SYSTEM IN ARTIFICIAL NEURAL NETWORK ARRAY
    11.
    发明公开
    VERIFICATION METHOD AND SYSTEM IN ARTIFICIAL NEURAL NETWORK ARRAY 审中-公开

    公开(公告)号：US20240104164A1

    公开(公告)日：2024-03-28

    申请号：US18080545

    申请日：2022-12-13

    Applicant: Silicon Storage Technology, Inc.

    Inventor： HIEU VAN TRAN ,  STEPHEN TRINH ,  STANLEY HONG ,  THUAN VU ,  DUC NGUYEN ,  HIEN HO PHAM

    IPC: G06F17/16 ,  G06N3/063

    CPC classification number: G06F17/16 ,  G06N3/063

    Abstract: Numerous examples are disclosed of verification circuitry and associated methods in an artificial neural network. In one example, a system comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells respectively capable of storing one of N possible levels corresponding to one of N possible currents, and a plurality of output blocks to receive current from respective columns of the vector-by-matrix multiplication array and generate voltages during a verify operation of the vector-by-matrix multiplication and generate digital outputs during a read operation of the vector-by-matrix multiplication.

    Memory Cell With Floating Gate, Coupling Gate And Erase Gate, And Method Of Making Same
    12.
    发明申请
    Memory Cell With Floating Gate, Coupling Gate And Erase Gate, And Method Of Making Same 审中-公开

    公开(公告)号：US20200176460A1

    公开(公告)日：2020-06-04

    申请号：US16208297

    申请日：2018-12-03

    Applicant: Silicon Storage Technology, Inc.

    Inventor： CATHERINE DECOBERT ,  HIEU VAN TRAN ,  NHAN DO

    IPC: H01L27/11521 ,  G11C16/26 ,  G11C16/16 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10

    Abstract: A memory device that includes source and drain regions formed in a semiconductor substrate, with a first channel region of the substrate extending there between. A floating gate is disposed over and insulated from the channel region, wherein the conductivity of the channel region is solely controlled by the floating gate. A control gate is disposed over and insulated from the floating gate. An erase gate is disposed over and insulated from the source region, wherein the erase gate includes a notch that faces and is insulated from an edge of the floating gate. Logic devices are formed on the same substrate. Each logic device has source and drain regions with a channel region extending there between, and a logic gate disposed over and controlling the logic device's channel region.

    High Density Split-Gate Memory Cell
    13.
    发明申请
    High Density Split-Gate Memory Cell 审中-公开

    公开(公告)号：US20190172529A1

    公开(公告)日：2019-06-06

    申请号：US16273337

    申请日：2019-02-12

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do ,  XIAN LIU ,  VIPIN TIWARI ,  HIEU VAN TRAN

    IPC: G11C11/419 ,  H01L29/788 ,  H01L29/66 ,  G11C16/14 ,  G11C16/04 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11521

    Abstract: A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.

    OUTPUT CIRCUIT FOR ARTIFICIAL NEURAL NETWORK ARRAY
    14.
    发明公开
    OUTPUT CIRCUIT FOR ARTIFICIAL NEURAL NETWORK ARRAY 审中-公开

    公开(公告)号：US20240112003A1

    公开(公告)日：2024-04-04

    申请号：US18077993

    申请日：2022-12-08

    Applicant: Silicon Storage Technology, Inc.

    Inventor： HIEU VAN TRAN ,  STEPHEN TRINH ,  STANLEY HONG ,  THUAN VU ,  NGHIA LE ,  HIEN PHAM

    IPC: G06N3/063 ,  G06F5/01 ,  G06F7/501

    CPC classification number: G06N3/063 ,  G06F5/01 ,  G06F7/501

    Abstract: Numerous examples are disclosed of output circuitry and associated methods in an artificial neural network. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, an output block to convert current from columns of the array into a first digital output during a first time period and a second digital output during a second time period, a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period, and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period.

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