公开(公告)号：US12255182B2

公开(公告)日：2025-03-18

申请号：US18235079

申请日：2023-08-17

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Meng-Huan Chia ,  Yih-Jenn Jiang ,  Chang-Fu Lin ,  Don-Son Jiang

IPC: H01L25/00 ,  H01L25/065 ,  H01L25/16

Abstract: An electronic package is provided, in which a first electronic element and a second electronic element are disposed on a first side of a circuit structure and a second side of the circuit structure, respectively, where a first metal layer is formed between the first side of the circuit structure and the first electronic element, a second metal layer is formed on a surface of the second electronic element, and at least one thermally conductive pillar is disposed on the second side of the circuit structure and extends into the circuit structure to thermally conduct the first metal layer and the second metal layer. Therefore, through the thermally conductive pillar, heat generated during operations of the first electronic element and the second electronic element can be quickly dissipated to an external environment and would not accumulate.

公开(公告)号：US12107055B2

公开(公告)日：2024-10-01

申请号：US18109120

申请日：2023-02-13

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chih-Hsun Hsu ,  Chi-Jen Chen ,  Hsi-Chang Hsu ,  Yuan-Hung Hsu ,  Rui-Feng Tai ,  Don-Son Jiang

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3157 ,  H01L24/05 ,  H01L25/0655 ,  H01L25/50 ,  H01L24/16 ,  H01L2224/05556 ,  H01L2224/16227

Abstract: An electronic package is provided and includes at least one protective structure positioned between a first electronic element and a second electronic element on a carrier for reducing stresses generated inside the first electronic element and the second electronic element when a filling material is formed on the carrier, encapsulates the protective structure and comes into contact with the first electronic element and the second electronic element, thereby preventing cracking of the first electronic element and the second electronic element and improving the reliability of the electronic package.

公开(公告)号：US11532528B2

公开(公告)日：2022-12-20

申请号：US17160720

申请日：2021-01-28

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chi-Jen Chen ,  Hsi-Chang Hsu ,  Yuan-Hung Hsu ,  Chang-Fu Lin ,  Don-Son Jiang

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

Abstract: An electronic package and a method for manufacturing the electronic package are provided. The method includes forming a slope surface on at least one side surface of at least one of a plurality of electronic components, and then disposing the plurality of electronic components on a carrier structure, such that the two adjacent electronic components form a space by the slope surface. Afterwards, an encapsulation layer is formed on the carrier structure and filled into the space to cover the two adjacent electronic components so as to disperse stress on the electronic components through the design of the space to prevent cracking due to stress concentration.

公开(公告)号：US20220148975A1

公开(公告)日：2022-05-12

申请号：US17134925

申请日：2020-12-28

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Wei-Jhen Chen ,  Chih-Hsun Hsu ,  Yuan-Hung Hsu ,  Chih-Nan Lin ,  Chang-Fu Lin ,  Don-Son Jiang ,  Chih-Ming Huang ,  Yi-Hsin Chen

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00

Abstract: An electronic package and a manufacturing method thereof, which embeds an electronic structure acting as an auxiliary functional component and a plurality of conductive pillars in an encapsulation layer, and disposes an electronic component on the encapsulation layer, so as to facilitate electrical transmission with the electronic component in a close range.

公开(公告)号：US10163662B2

公开(公告)日：2018-12-25

申请号：US15478508

申请日：2017-04-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Cheng-Chia Chiang ,  Don-Son Jiang ,  Lung-Yuan Wang ,  Shih-Hao Tung ,  Shu-Huei Huang

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538

Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.

公开(公告)号：US09673140B2

公开(公告)日：2017-06-06

申请号：US14620328

申请日：2015-02-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chia-Cheng Chen ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Yu-Cheng Pai ,  Don-Son Jiang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/16

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/15156 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/19103 ,  H01L2924/37001 ,  H01L2924/014

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a laminate on the carrier, wherein the laminate has a built-up portion and a release portion smaller in size than the built-up portion, the release portion covering the bonding pads and the built-up portion being laminated on the release portion and the carrier; forming a plurality of conductive posts in the built-up portion; and removing the release portion and the built-up portion on the release portion such that a cavity is formed in the laminate to expose the bonding pads, the conductive posts being positioned around a periphery of the cavity. Therefore, the present invention has simplified processes.

公开(公告)号：US20150287671A1

公开(公告)日：2015-10-08

申请号：US14620328

申请日：2015-02-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chia-Cheng Chen ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Yu-Cheng Pai ,  Don-Son Jiang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/492

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/15156 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/19103 ,  H01L2924/37001 ,  H01L2924/014

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a laminate on the carrier, wherein the laminate has a built-up portion and a release portion smaller in size than the built-up portion, the release portion covering the bonding pads and the built-up portion being laminated on the release portion and the carrier; forming a plurality of conductive posts in the built-up portion; and removing the release portion and the built-up portion on the release portion such that a cavity is formed in the laminate to expose the bonding pads, the conductive posts being positioned around a periphery of the cavity. Therefore, the present invention has simplified processes.

Abstract translation: 提供了一种制造封装结构的方法，其包括以下步骤：提供具有多个焊盘的载体; 在载体上层叠层压体，其中层压体具有积累部分和尺寸小于组合部分的剥离部分，覆盖接合焊盘的释放部分和积层部分层压在释放部分上， 承运人 在所述积层部中形成多个导电柱; 以及在所述释放部分上移除所述释放部分和所述积累部分，使得在所述层压体中形成空腔以露出所述接合焊盘，所述导电柱位于所述空腔的周边周围。 因此，本发明具有简化的处理。

公开(公告)号：US20150187722A1

公开(公告)日：2015-07-02

申请号：US14255326

申请日：2014-04-17

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Cheng-Chia Chiang ,  Don-Son Jiang ,  Lung-Yuan Wang ,  Shih-Hao Tung ,  Shu-Huei Huang

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.

Abstract translation: 提供一种半导体封装，其包括：具有相对的第一和第二表面的封装基板和形成在第一表面上的多个第一和第二导电焊盘; 具有相反的有源和无源表面的芯片，并经由其主动表面设置在第一导电焊盘上; 分别形成在所述第二导电焊盘上的多个导电柱; 以及形成在所述封装基板的所述第一表面上的第一密封剂，用于封装所述芯片和所述导电柱，并且具有用于暴露所述导电柱的上表面的多个开口，从而增加所述封装密度并保护所述芯片和所述互连结构 受到水分侵入的不利影响。

公开(公告)号：US20240321798A1

公开(公告)日：2024-09-26

申请号：US18602396

申请日：2024-03-12

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chi-Ren Chen ,  Po-Yung Chang ,  Pei-Geng Weng ,  Yuan-Hung Hsu ,  Chang-Fu Lin ,  Don-Son Jiang

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L21/56 ,  H01L23/31 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562

Abstract: An electronic package is provided and includes a carrier for carrying electronic components. Electrical contact pads of the carrier for planting solder balls are connected with a plurality of columnar conductors, and the conductors are electrically connected to a circuit portion in the carrier. By connecting a plurality of conductors with a single electrical contact pad, structural stress can be distributed and breakage of the circuit portion can be prevented.

公开(公告)号：US11764188B2

公开(公告)日：2023-09-19

申请号：US17411228

申请日：2021-08-25

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Meng-Huan Chia ,  Yih-Jenn Jiang ,  Chang-Fu Lin ,  Don-Son Jiang

IPC: H01L25/065 ,  H01L25/16 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/162 ,  H01L25/50 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589

Abstract: An electronic package is provided, in which a first electronic element and a second electronic element are disposed on a first side of a circuit structure and a second side of the circuit structure, respectively, where a first metal layer is formed between the first side of the circuit structure and the first electronic element, a second metal layer is formed on a surface of the second electronic element, and at least one thermally conductive pillar is disposed on the second side of the circuit structure and extends into the circuit structure to thermally conduct the first metal layer and the second metal layer. Therefore, through the thermally conductive pillar, heat generated during operations of the first electronic element and the second electronic element can be quickly dissipated to an external environment and would not accumulate.