公开(公告)号：US12198983B2

公开(公告)日：2025-01-14

申请号：US17756615

申请日：2020-10-26

Applicant: Soitec

Inventor： Ionut Radu ,  Hugo Biard ,  Christophe Maleville ,  Eric Guiot ,  Didier Landru

IPC: H01L21/78 ,  C23C16/32 ,  C30B25/20 ,  C30B29/36 ,  C30B31/22 ,  C30B33/10 ,  H01L21/02

Abstract: A method of producing a composite structure comprising a thin layer of monocrystalline silicon carbide arranged on a carrier substrate of silicon carbide comprises: a) a step of provision of an initial substrate of monocrystalline silicon carbide, b) a step of epitaxial growth of a donor layer of monocrystalline silicon carbide on the initial substrate, to form a donor substrate, c) a step of ion implantation of light species into the donor layer, to form a buried brittle plane delimiting the thin layer, d) a step of formation of a carrier substrate of silicon carbide on the free surface of the donor layer, comprising a deposition at a temperature of between 400° C. and 1100° C., e) a step of separation along the buried brittle plane, to form the composite structure and the remainder of the donor substrate, and f) a step of chemical-mechanical treatment(s) of the composite structure.

公开(公告)号：US20230411140A1

公开(公告)日：2023-12-21

申请号：US18248169

申请日：2021-10-04

Applicant: Soitec

Inventor： Eric Guiot

IPC: H01L21/02 ,  H01L29/66 ,  C30B31/22 ,  C30B29/36 ,  C30B29/40 ,  C30B25/18

CPC classification number: H01L21/02002 ,  H01L29/66462 ,  H01L21/0254 ,  H01L21/02378 ,  C30B31/22 ,  C30B29/36 ,  C30B29/406 ,  C30B25/186

Abstract: A method of producing a substrate for epitaxial growth of a gallium-based III-N alloy layer comprises the following consecutive steps: —providing a donor substrate of semi-insulating monocrystalline silicon carbide, —implanting ionic species in the donor substrate so as to form a zone of weakness defining a thin layer of semi-insulating monocrystalline SiC to be transferred, —bonding the donor substrate to a first receiving substrate by means of a bonding layer, —detaching the donor substrate along the zone of weakness so as to transfer the thin layer of semi-insulating monocrystalline SiC on to the first receiving substrate, —forming an additional layer of semi-insulating SiC on the transferred thin layer, —bonding the additional layer to a second receiving substrate having a high electrical resistivity, —removing at least a portion of the bonding layer so as to detach the first receiving substrate and expose the layer of transferred semi-insulating monocrystalline SiC.

公开(公告)号：US11251321B2

公开(公告)日：2022-02-15

申请号：US16074342

申请日：2017-01-27

Applicant: Soitec ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Eric Guiot ,  Aurelie Tauzin ,  Thomas Signamarcheix ,  Emmanuelle Lagoutte

IPC: H01L31/043 ,  H01L31/18 ,  H01L31/0725 ,  H01L31/054 ,  H01L21/18 ,  H01L31/0735

Abstract: An engineered substrate comprising: a seed layer made of a first semiconductor material for growth of a solar cell; a first bonding layer on the seed layer; a support substrate made of a second semiconductor material; a second bonding layer on a first side of the support substrate; a bonding interface between the first and second bonding layers; the first and second bonding layers each made of metallic material; wherein doping concentration and thickness of the engineered substrate, in particular, of the seed layer, the support substrate, and both the first and second bonding layers, are selected such that the absorption of the seed layer is less than 20%, preferably less than 10%, as well as total area-normalized series resistance of the engineered substrate is less than 10 mOhm·cm2, preferably less than 5 mOhm·cm2.

公开(公告)号：US09136113B2

公开(公告)日：2015-09-15

申请号：US14044846

申请日：2013-10-02

Applicant: SOITEC

Inventor： Didier Landru ,  Fabrice Gritti ,  Eric Guiot ,  Oleg Kononchuk ,  Christelle Veytizou

IPC: H01L21/461 ,  H01L21/02 ,  H01L21/316 ,  H01L21/324 ,  H01L21/762

CPC classification number: H01L21/3247 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/31662 ,  H01L21/7624

Abstract: A process for avoiding formation of an Si—SiO2—H2 environment during a dissolution treatment of a semiconductor-on-insulator structure that includes a carrier substrate, an oxide layer, a thin layer of a semiconductor material and a peripheral ring in which the oxide layer is exposed. This process includes encapsulating at least the exposed oxide layer of the peripheral ring with semiconductor material by performing a creep thermal treatment; and performing an oxide dissolution treatment to reduce part of the thickness of the oxide layer. In this process, the semiconductor material that encapsulates the oxide layer has a thickness before the oxide dissolution that is at least twice that of the oxide that is to be dissolved, thus avoiding formation of an Si—SiO2—H2 environment on the peripheral ring where the oxide layer would otherwise be exposed.

Abstract translation: 在绝缘体上半导体结构的溶解处理中避免形成Si-SiO 2 -H 2环境的方法，其包括载体衬底，氧化物层，半导体材料的薄层和外围环，其中氧化物 层暴露。 该方法包括通过进行蠕变热处理将至少外围环的暴露的氧化物层与半导体材料封装起来; 并进行氧化物溶解处理以减少氧化物层的厚度的一部分。 在该方法中，封装氧化物层的半导体材料的氧化物溶解前的厚度为要溶解的氧化物的至少两倍，因此避免在外围环上形成Si-SiO 2 -H 2环境， 否则会暴露氧化层。

公开(公告)号：US20240271321A1

公开(公告)日：2024-08-15

申请号：US18693491

申请日：2022-09-13

Applicant: Soitec

Inventor： Frédéric Allibert ,  Eric Guiot

IPC: C30B25/20 ,  C30B28/14 ,  C30B29/36

CPC classification number: C30B25/20 ,  C30B28/14 ,  C30B29/36

Abstract: A method of fabricating a composite structure includes providing a c-SiC initial substrate, depositing a relatively thin p-SiC first layer on a front side of the initial substrate at a relatively high temperature, the first layer having a dopant concentration greater than 1019/cm3, forming a buried brittle plane in the initial substrate delineating a thin layer of single crystal SiC between the brittle plane and a front side of the initial substrate, depositing a relatively thick amorphous and/or polycrystalline SiC second layer on the first layer at a relatively low temperature, the second layer including dopants of the same type as those of the first layer, at a concentration greater than 1019/cm3, and depositing a p-SiC third layer on the second layer at a relatively high temperature. A separation along the buried brittle plane takes place during the deposition process.

公开(公告)号：US20240266172A1

公开(公告)日：2024-08-08

申请号：US18004594

申请日：2021-06-08

Applicant: Commissariat À L'énergie Atomique Et Aux Énergies Alternatives ,  Soitec

Inventor： Frédéric Allibert ,  Didier Landru ,  Oleg Kononchuk ,  Eric Guiot ,  Gweltaz Gaudin ,  Julie Widiez ,  Franck Fournel

IPC: H01L21/18 ,  H01L21/02 ,  H01L21/04 ,  H01L21/324 ,  H01L23/00

CPC classification number: H01L21/187 ,  H01L21/02016 ,  H01L21/0485 ,  H01L21/324 ,  H01L24/83 ,  H01L2224/83894 ,  H01L2224/83948 ,  H01L2924/10253 ,  H01L2924/10272

Abstract: The invention relates to a semiconductor structure (100) that comprises a useful layer (10) made of monocrystalline semiconductor material and extending along a main plane (x, y), a support substrate (30) made of semiconductor material, and an interface area (20) between the useful layer (10) and the support substrate (30), the support substrate extending parallel to the main plane (x, y), the structure (100) being characterised in that the interface area (20) comprises nodules (21) that:—are electrically conductive, in that they contain a metal material forming ohmic contact with the useful layer (10) and the support substrate (30);—have a thickness, along an axis (z) normal to the main plane (x, y) , of less than or equal to 30 nm;—are separate or adjoining, the separate nodules (21) being separated from each other by regions (22) of direct contact between the useful layer (10) and the support substrate (30). The invention also relates to a method for manufacturing the structure (100).