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89 条记录 (耗时 0.033 秒)

    FinFET diode with increased junction area
    11.
    发明授权
    FinFET diode with increased junction area 失效
    FinFET二极管具有增加的接合面积

    公开(公告)号：US08592263B2

    公开(公告)日：2013-11-26

    申请号：US13456921

    申请日：2012-04-26

    申请人： Theodorus Eduardus Standaert ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Tenko Yamashita

    发明人： Theodorus Eduardus Standaert ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Tenko Yamashita

    IPC分类号： H01L21/84

    CPC分类号： H01L29/861 ,  H01L21/845 ,  H01L27/0266 ,  H01L29/24 ,  H01L29/267 ,  H01L29/6609 ,  H01L29/785

    摘要： A FinFET diode and method of fabrication are disclosed. In one embodiment, the diode comprises, a semiconductor substrate, an insulator layer disposed on the semiconductor substrate, a first silicon layer disposed on the insulator layer, a plurality of fins formed in a diode portion of the first silicon layer. A region of the first silicon layer is disposed adjacent to each of the plurality of fins. A second silicon layer is disposed on the plurality of fins formed in the diode portion of the first silicon layer. A gate ring is disposed on the first silicon layer. The gate ring is arranged in a closed shape, and encloses a portion of the plurality of fins formed in the diode portion of the first silicon layer.

    摘要翻译： 公开了一种FinFET二极管及其制造方法。 在一个实施例中，二极管包括半导体衬底，设置在半导体衬底上的绝缘体层，设置在绝缘体层上的第一硅层，形成在第一硅层的二极管部分中的多个鳍片。 第一硅层的区域设置成与多个翅片中的每一个相邻。 第二硅层设置在形成在第一硅层的二极管部分中的多个翅片上。 栅极环设置在第一硅层上。 门环布置成闭合形状，并且包围形成在第一硅层的二极管部分中的多个翅片的一部分。

    MOSFET including asymmetric source and drain regions
    13.
    发明授权
    MOSFET including asymmetric source and drain regions 失效
    MOSFET包括不对称的源极和漏极区域

    公开(公告)号：US08772874B2

    公开(公告)日：2014-07-08

    申请号：US13216554

    申请日：2011-08-24

    申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

    CPC分类号： H01L29/66477 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/84 ,  H01L29/66045 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66803 ,  H01L29/785

    摘要： At least one drain-side surfaces of a field effect transistor (FET) structure, which can be a structure for a planar FET or a fin FET, is structurally damaged by an angled ion implantation of inert or electrically active dopants, while at least one source-side surface of the transistor is protected from implantation by a gate stack and a gate spacer. Epitaxial growth of a semiconductor material is retarded on the at least one structurally damaged drain-side surface, while epitaxial growth proceeds without retardation on the at least one source-side surface. A raised epitaxial source region has a greater thickness than a raised epitaxial drain region, thereby providing an asymmetric FET having lesser source-side external resistance than drain-side external resistance, and having lesser drain-side overlap capacitance than source-side overlap capacitance.

    摘要翻译： 作为平面FET或鳍式FET的结构的场效应晶体管（FET）结构的至少一个漏极侧表面在结构上被惰性或电活性掺杂剂的成角度的离子注入损坏，而至少一个 保护晶体管的源极侧表面不被栅极堆叠和栅极间隔物的注入。 半导体材料的外延生长在至少一个结构损坏的漏极侧表面上延迟，而外延生长在至少一个源极侧表面上没有延迟。 凸起的外延源区域具有比凸起的外延漏极区域更大的厚度，从而提供具有比漏极侧外部电阻更小的源极侧外部电阻并且具有比源极重叠电容更少的漏极侧重叠电容的非对称FET。

    SOI DEVICE WITH EMBEDDED LINER IN BOX LAYER TO LIMIT STI RECESS
    14.
    发明申请
    SOI DEVICE WITH EMBEDDED LINER IN BOX LAYER TO LIMIT STI RECESS 有权
    具有嵌入式衬垫的SOI器件限制STI感染

    公开(公告)号：US20140070357A1

    公开(公告)日：2014-03-13

    申请号：US13611182

    申请日：2012-09-12

    申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth

    发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth

    IPC分类号： H01L29/06 ,  H01L21/762

    CPC分类号： H01L27/1203 ,  H01L21/31144 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/06 ,  H01L29/66772 ,  H01L29/78654

    摘要： A semiconductor substrate having an isolation region and method of forming the same. The method includes the steps of providing a substrate having a substrate layer, a buried oxide (BOX), a silicon on insulator (SOI) layer, a pad oxide layer, and a pad nitride layer, forming a shallow trench region, etching the pad oxide layer to form ears and etching the BOX layer to form undercuts, depositing a liner on the shallow trench region, depositing a soft mask over the surface of the shallow trench region, filling the shallow trench region, etching the soft mask so that it is recessed to the top of the BOX layer, etching the liner off certain regions, removing the soft mask, and filling and polishing the shallow trench region. The liner prevents shorting of the semiconductor device when the contacts are misaligned.

    摘要翻译： 具有隔离区域的半导体基板及其形成方法。 该方法包括以下步骤：提供具有衬底层，掩埋氧化物（BOX），绝缘体上硅（SOI）层，衬垫氧化物层和衬垫氮化物层的衬底，形成浅沟槽区，蚀刻衬垫 氧化层以形成耳朵并蚀刻BOX层以形成底切，在浅沟槽区域上沉积衬垫，在浅沟槽区域的表面上沉积软掩模，填充浅沟槽区域，蚀刻软掩模，使得它 凹陷到BOX层的顶部，在某些区域蚀刻衬垫，去除软掩模，以及填充和抛光浅沟槽区域。 当触点不对准时，衬垫防止半导体器件的短路。