公开(公告)号：US5032528A

公开(公告)日：1991-07-16

申请号：US538764

申请日：1990-06-15

申请人： Yoshiaki Asao ,  Shizuo Sawada

发明人： Yoshiaki Asao ,  Shizuo Sawada

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/768

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/31662 ,  H01L21/76802

摘要： Regions having different impurity concentrations are formed in the main surface region of the semiconductor substrate. Accordingly, when the substrate is oxidized, oxide films having different thickness are formed. More specifically, the oxide film is formed more deeply on the surface region of the substrate having a high impurity concentration in which ions are injected than on the surface region in which no ions are injected. In the etching step, since the thinner oxide film is removed while the thicker oxide film remains, the surface of the region under the thinner oxide film is exposed, and thus a contact hole is formed. If, in the step of forming a contact hole, a portion of the thinner oxide film is covered by a resist pattern, only the regiion of the oxide film which is not masked by the resist pattern is etched and the substrate surface thereunder is exposed, and thus a contact hole is formed.

公开(公告)号：US20060124980A1

公开(公告)日：2006-06-15

申请号：US11333412

申请日：2006-01-18

申请人： Yusuke Kohyama ,  Takashi Ohsawa ,  Shizuo Sawada

发明人： Yusuke Kohyama ,  Takashi Ohsawa ,  Shizuo Sawada

IPC分类号： H01L29/94

CPC分类号： H01L27/10888 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

摘要： First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.

公开(公告)号：US06252281B1

公开(公告)日：2001-06-26

申请号：US08612456

申请日：1996-03-07

申请人： Tadashi Yamamoto ,  Shizuo Sawada

发明人： Tadashi Yamamoto ,  Shizuo Sawada

IPC分类号： H01L2701

CPC分类号： H01L27/10894 ,  H01L21/76264 ,  H01L21/76281 ,  H01L27/10811 ,  H01L27/10873 ,  H01L27/1203

摘要： Silicon oxide layers are provided in a substrate. That part of the silicon oxide layer which is located in a memory cell section MC has a thickness. That part of the silicon oxide layer which is located in a peripheral circuit section PC has a thickness, which is less than the thickness. The memory cell section MC has transistors, each having a source region and a drain region which contact the silicon oxide layer. The peripheral circuit section PC has transistors, each having a source region and a drain region which are spaced apart from the silicon oxide layer. The transistors of the peripheral circuit section PC are provided in well regions. A back-gate bias is applied to the transistors of the peripheral circuit section PC through impurity layers.

摘要翻译： 氧化硅层设置在基板中。 位于存储单元部分MC中的部分氧化硅层具有厚度。 位于外围电路部分PC中的部分氧化硅层的厚度小于厚度。 存储单元部MC具有各自具有与氧化硅层接触的源极区域和漏极区域的晶体管。 外围电路部分PC具有各自具有与氧化硅层间隔开的源极区域和漏极区域的晶体管。 外围电路部分PC的晶体管设置在阱区中。 背栅极偏置通过杂质层施加到外围电路部分PC的晶体管。

公开(公告)号：US5410169A

公开(公告)日：1995-04-25

申请号：US20444

申请日：1993-02-22

申请人： Tadashi Yamamoto ,  Shizuo Sawada

发明人： Tadashi Yamamoto ,  Shizuo Sawada

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10808

摘要： There is provided a DRAM memory cell structure. The semiconductor structure includes a semiconductor substrate of a first conductivity type having a main surface, source and drain regions of a second conductivity type formed in the main surface area of the semiconductor substrate, word lines extending in a first plane direction and formed on those portions of the semiconductor substrate which respectively lie between the source and drain regions, capacitors each having one of the source and drain regions as a storage node electrode, and bit lines buried in the semiconductor substrate and electrically connected to the source or drain regions, respectively.

摘要翻译： 提供了DRAM存储单元结构。 半导体结构包括：第一导电类型的半导体衬底，具有主表面，形成在半导体衬底的主表面区域中的第二导电类型的源极和漏极区域，字线在第一平面方向上延伸并形成在这些部分上 分别位于源极和漏极区之间的半导体衬底，分别具有源极和漏极区之一的电容器作为存储节点电极，以及掩埋在半导体衬底中并分别电连接到源极或漏极区的位线。

公开(公告)号：US5302844A

公开(公告)日：1994-04-12

申请号：US15676

申请日：1993-02-09

申请人： Tomohisa Mizuno ,  Shizuo Sawada

发明人： Tomohisa Mizuno ,  Shizuo Sawada

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/92 ,  H01L29/94 ,  H01L27/02 ,  H01L29/68 ,  H01L29/78

CPC分类号： H01L27/10808 ,  H01L28/87 ,  H01L29/94

摘要： According to the present invention, a lower electrode is formed on a semiconductor substrate and overgrows upward to form one electrode of a capacitor having a mushroom-shaped section. An insulation film is formed so as to at least cover the lower electrode. An upper electrode is formed so as to oppose the lower electrode and to cover at least the insulation film.

摘要翻译： 根据本发明，在半导体基板上形成下电极，向上方向上形成具有蘑菇形截面的电容器的一个电极。 形成绝缘膜至少覆盖下电极。 上电极形成为与下电极相对并且至少覆盖绝缘膜。

公开(公告)号：US5041887A

公开(公告)日：1991-08-20

申请号：US522796

申请日：1990-05-14

申请人： Jumpei Kumagai ,  Shizuo Sawada

发明人： Jumpei Kumagai ,  Shizuo Sawada

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10829

摘要： In one-transistor.one-capacitor type dynamic memory cell, cell capacitor with a reduced junction leakage current comprises a MOS capacitor which is provided between a semiconductor substrate and a charge storage electrode disposed at a side wall of a trench through a first insulating film, and a stacked capacitor which is provided between the charge storage electrode and a capacitor plate electrode formed on a second insulating film covering the entire surface of the charge storage electrode. The equivalent silicon dioxide thickness of the first insulating film is thicker than that of the second insulating film, and the storage capacitance of the cell capacitor is rendered by a sum of the capacitance of the MOS capacitor and the capacitance of the stacked capacitor because these capacitors are electrically connected in parallel with each other.

公开(公告)号：US5004704A

公开(公告)日：1991-04-02

申请号：US428903

申请日：1989-10-30

申请人： Satoshi Maeda ,  Shizuo Sawada

发明人： Satoshi Maeda ,  Shizuo Sawada

IPC分类号： H01L21/3205 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/52

CPC分类号： H01L21/76837 ,  H01L21/31051 ,  H01L21/76834 ,  Y10S148/133

摘要： A Phospho Silicate Glass layer is used for an insulation layer between a lower wiring layer including a refractory metal silicide and an upper wiring layer in a semiconductor device of a multilevel interconnection structure. A reflow treatment is performed on the Phospho Silicate Glass layer using steam. A part of the lower wiring layer is oxidized during the reflow treatment, and the resistivity of the lower wiring layer is simultaneously lowered during the reflow treatment.

公开(公告)号：US4410375A

公开(公告)日：1983-10-18

申请号：US307875

申请日：1981-10-02

申请人： Shizuo Sawada ,  Hiroshi Iwai ,  Satoshi Maeda

发明人： Shizuo Sawada ,  Hiroshi Iwai ,  Satoshi Maeda

IPC分类号： H01L27/10 ,  H01L21/225 ,  H01L21/3105 ,  H01L21/322 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L21/2255 ,  H01L21/3105 ,  H01L27/10805

摘要： A method for fabricating a semiconductor device is disclosed which includes a step of forming contact holes in insulating films on a substrate, forming a silicate glass layer containing an impurity over the entire surface, and performing the phosphorus getter treatment using POCl.sub.3 at a high temperature. Even when the phosphorus getter treatment is performed after the formation of the contact holes, the substrate or electrodes exposed through the contact holes may not be reduced in thickness or damaged. The impurity may be diffused into the substrate from the silicate glass layer through the contact holes.

摘要翻译： 公开了一种制造半导体器件的方法，其包括在基片上形成绝缘膜中的接触孔的步骤，在整个表面上形成含有杂质的硅酸盐玻璃层，并在高温下使用POCl 3进行磷吸气剂处理。 即使在形成接触孔之后进行磷吸气剂处理，也可能不会使通过接触孔露出的基板或电极的厚度减小或损坏。 杂质可以从硅酸盐玻璃层通过接触孔扩散到衬底中。

公开(公告)号：US07187027B2

公开(公告)日：2007-03-06

申请号：US11333412

申请日：2006-01-18

申请人： Yusuke Kohyama ,  Takashi Ohsawa ,  Shizuo Sawada

发明人： Yusuke Kohyama ,  Takashi Ohsawa ,  Shizuo Sawada

IPC分类号： H01L27/108

CPC分类号： H01L27/10888 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

摘要： First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.

摘要翻译： 第一和第二布线形成在第一绝缘膜上。 每个布线被布置成使得导电膜，氧化硅膜和氮化硅膜层压。 此后，在整个表面上形成氧化硅绝缘膜。 蚀刻氧化硅绝缘膜，使得在第一和第二布线之间形成接触孔。 由于在每个布线的导电膜上存在氧化硅膜和氮化硅膜，因此在蚀刻时导电膜不会露出。 此后，在接触孔的侧壁上形成绝缘膜，并且通过接触孔露出的导电膜被绝缘膜覆盖。

公开(公告)号：US06551894B1

公开(公告)日：2003-04-22

申请号：US09631830

申请日：2000-08-03

申请人： Yusuke Kohyama ,  Takashi Ohsawa ,  Shizuo Sawada

发明人： Yusuke Kohyama ,  Takashi Ohsawa ,  Shizuo Sawada

IPC分类号： H01L2120

CPC分类号： H01L27/10888 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

摘要： First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.

摘要翻译： 第一和第二布线形成在第一绝缘膜上。 每个布线被布置成使得导电膜，氧化硅膜和氮化硅膜层压。 此后，在整个表面上形成氧化硅绝缘膜。 蚀刻氧化硅绝缘膜，使得在第一和第二布线之间形成接触孔。 由于在每个布线的导电膜上存在氧化硅膜和氮化硅膜，因此在蚀刻时导电膜不会露出。 此后，在接触孔的侧壁上形成绝缘膜，并且通过接触孔露出的导电膜被绝缘膜覆盖。