公开(公告)号：US11436024B2

公开(公告)日：2022-09-06

申请号：US16700254

申请日：2019-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Denis Roland Beaudoin ,  Gregory Raymond Shurtz ,  Santhanakrishnan Badri Narayanan ,  Mark Adrian Bryans ,  Mihir Narendra Mody ,  Jason A. T. Jones ,  Jayant Thakur

IPC: G06F9/4401 ,  H04L45/00 ,  H04L47/32 ,  G06F13/28 ,  H04L49/351

Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.

公开(公告)号：US20210263883A1

公开(公告)日：2021-08-26

申请号：US17314313

申请日：2021-05-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jason A.T. Jones ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  Kishon Vijay Abraham Israel Vijayponraj ,  Bradley Douglas Cobb ,  Sanand Prasad ,  Gregory Raymond Shurtz ,  Martin Jeffrey Ambrose ,  Jayant Thakur

IPC: G06F15/78 ,  G06F13/10

Abstract: An integrated circuit. The integrated circuit comprises an interconnect communication bus and a plurality of peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP comprising a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and a plurality of base address registers (BARs).

公开(公告)号：US11030144B2

公开(公告)日：2021-06-08

申请号：US16221364

申请日：2018-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jason A. T. Jones ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  Kishon Vijay Abraham Israel Vijayponraj ,  Bradley Douglas Cobb ,  Sanand Prasad ,  Gregory Raymond Shurtz ,  Martin Jeffrey Ambrose ,  Jayant Thakur

IPC: G06F15/78 ,  G06F13/10

Abstract: An integrated circuit. The integrated circuit comprises an interconnect communication bus and a plurality of peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP comprising a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and a plurality of base address registers (BARs).

公开(公告)号：US11027656B1

公开(公告)日：2021-06-08

申请号：US16709548

申请日：2019-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajat Sagar ,  Mihir Narendra Mody ,  Anthony Joseph Lell ,  Gregory Raymond Shurtz

IPC: H04N21/2343 ,  B60R1/00 ,  H04N5/225

Abstract: A hub that receives sensor data streams and then distributes the data streams to the various systems that use the sensor data. A demultiplexer (demux) receives the streams, filters out undesired streams and provides desired streams to the proper multiplexer (mux) or muxes of a series of muxes. Each mux combines received streams and provides an output stream to a respective formatter or output block. The formatter or output block is configured based on the destination of the mux output stream, such as an image signal processor, a processor, memory or external transmission. The output block reformats the received stream to a format appropriate for the recipient and then provides the reformatted stream to that recipient.

公开(公告)号：US20190043153A1

公开(公告)日：2019-02-07

申请号：US15668453

申请日：2017-08-03

Applicant: Texas Instruments Incorporated

Inventor： Sunita Nadampalli ,  Anish Reghunath ,  Brian Okchon Chae ,  Jonathan Elliot Bergsagel ,  Gregory Raymond Shurtz

IPC: G06T1/20 ,  G06F3/06 ,  G06F9/54 ,  H04N21/4143

CPC classification number: G06T1/20 ,  G06F3/0641 ,  G06F3/0655 ,  G06F9/544 ,  H04N21/41422 ,  H04N21/4143 ,  H04N21/42653 ,  H04N2005/443

Abstract: An integrated circuit includes a display sub-system that has a plurality of image processing resources and control logic. The image processing resources include a plurality of image processing pipelines configured to operate in parallel, overlay logic coupled to receive image data from the plurality of image processing pipelines, and an image output port coupled to an output of the overlay logic with image data outputs configured to couple to one or more display devices. The control logic is dynamically configurable to assign each of the image processing resources to a selected one of a first control port and a second control port. The first control port is configured to be controlled exclusively by a first processor and the second control port is configured to be controlled exclusively by a second processor.

公开(公告)号：US12013931B2

公开(公告)日：2024-06-18

申请号：US17550948

申请日：2021-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kedar Satish Chitnis ,  Mihir Narendra Mody ,  Amritpal Singh Mundra ,  Yashwant Dutt ,  Gregory Raymond Shurtz ,  Robert John Tivy

IPC: G06F21/54 ,  G06F9/48 ,  G06F21/55 ,  G06F21/79

CPC classification number: G06F21/54 ,  G06F9/485 ,  G06F21/554 ,  G06F21/79

Abstract: A method of enabling memory access freedom from interference (FFI) rules, comprising: determining a first safety privilege access ID (PrivID) for a first component of a system (e.g., based on Automotive Safety Integrity Level (ASIL) attributes of tasks executed by the first component); determining a first access attribute for a first software task executing on the first component; receiving, at a first firewall component of the system, a request from the first software task to access a first memory region of a second component of the system, wherein the request specifies the first PrivID and the first access attribute; and determining, by the first firewall component, whether to permit the first software task to access the first memory region based on the first PrivID, the first access attribute, and the first memory region.

公开(公告)号：US11853772B2

公开(公告)日：2023-12-26

申请号：US17888533

申请日：2022-08-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Denis Roland Beaudoin ,  Gregory Raymond Shurtz ,  Santhanakrishnan Badri Narayanan ,  Mark Adrian Bryans ,  Mihir Narendra Mody ,  Jason A. T. Jones ,  Jayant Thakur

IPC: G06F9/4401 ,  H04L45/00 ,  H04L47/32 ,  G06F13/28 ,  H04L49/351

CPC classification number: G06F9/4418 ,  G06F9/4406 ,  G06F13/28 ,  H04L45/54 ,  H04L45/66 ,  H04L47/32 ,  H04L49/351

Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.

公开(公告)号：US11715188B1

公开(公告)日：2023-08-01

申请号：US17682735

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Veeramanikandan Raju ,  Niraj Nandan ,  Samuel Paul Visalli ,  Jason A. T. Jones ,  Kedar Satish Chitnis ,  Gregory Raymond Shurtz ,  Prithvi Shankar Yeyyadi Anantha ,  Sriramakrishnan Govindarajan

IPC: G05B23/02 ,  G06T1/20 ,  G06T7/00 ,  G06T3/40 ,  H04N17/00

CPC classification number: G06T7/0002 ,  G05B23/0259 ,  G06T1/20 ,  G06T3/40 ,  G06T7/97 ,  G06T2207/10016 ,  H04N17/00

Abstract: An electronic device may be configured to detect a fault in imaging and vision hardware accelerators. The electronic device may include a controller configured to select a first golden input frame of multiple golden input frames to perform a first self-test, and retrieve a first reference image signature corresponding to the first golden input frame. The electronic device may include a hardware accelerator module configured to obtain the first golden input frame, and generate a first output frame based on the first golden input frame. The electronic device may include a signature generator configured to generate a first generated image signature based on the first output frame. The electronic device may include a signature comparison module configured to compare the first generated image signature to the first reference image signature in order to determine whether the hardware accelerator module includes a fault at a first time.

公开(公告)号：US20210117254A1

公开(公告)日：2021-04-22

申请号：US17138036

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Kedar Satish Chitnis ,  Charles Lance Fuoco ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  William A. Mills ,  Gregory Raymond Shurtz ,  Amritpal Singh Mundra

IPC: G06F9/54 ,  G06F9/50 ,  G06F9/38 ,  G06F9/455 ,  G06F9/48

Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.