公开(公告)号：US20240339457A1

公开(公告)日：2024-10-10

申请号：US18748862

申请日：2024-06-20

Applicant: Texas Instruments Incorporated

Inventor： Honglin Guo ,  Frank John Sweeney

IPC: H01L27/12 ,  H01L21/265 ,  H01L23/00 ,  H01L29/94 ,  H01L33/64

CPC classification number: H01L27/1203 ,  H01L23/564 ,  H01L21/26513 ,  H01L29/94 ,  H01L33/645

Abstract: An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer. An electronic device has an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A white space region adjacent the electronic device includes a first P-type region in the semiconductor layer and adjacent the surface. The P-type region has a first sheet resistance and the NWELL region has a second sheet resistance that is greater than the first sheet resistance.

公开(公告)号：US20240145603A1

公开(公告)日：2024-05-02

申请号：US18408001

申请日：2024-01-09

Applicant: Texas Instruments Incorporated

Inventor： Honglin Guo ,  Zachary K. Lee ,  Jingjing Chen

IPC: H01L29/94 ,  H01L29/66

CPC classification number: H01L29/94 ,  H01L29/66189 ,  H01L21/26586

Abstract: An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer; the semiconductor layer contains white space regions that include a PWELL region. An electronic device includes an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A sacrificial NWELL ring is adjacent to and separated from the NWELL region by a first gap.

公开(公告)号：US11881462B2

公开(公告)日：2024-01-23

申请号：US17034435

申请日：2020-09-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Honglin Guo

IPC: H01L23/64 ,  H01L27/08 ,  H01L23/522 ,  H01L21/82 ,  H01L27/01

CPC classification number: H01L23/642 ,  H01L21/82 ,  H01L23/5223 ,  H01L27/01 ,  H01L27/0805

Abstract: A semiconductor device includes an impedance having a first port and a second port located over a semiconductor substrate. The impedance includes at least one metal-insulator-metal (MIM) lateral flux capacitor (LFC) pair. Each LFC pair includes a first LFC connected in series with a second LFC. A terminal of the first LFC is connected to the first port, and a terminal of the second LFC is connected to the second port. Optionally the device further includes circuitry formed over the semiconductor substrate, wherein the circuitry is configured to implement a circuit function in cooperation with the impedance.

公开(公告)号：US20230253407A1

公开(公告)日：2023-08-10

申请号：US17665501

申请日：2022-02-05

Applicant: Texas Instruments Incorporated

Inventor： Honglin Guo ,  Frank John Sweeney

IPC: H01L27/12 ,  H01L23/00

CPC classification number: H01L27/1203 ,  H01L23/564 ,  H01L21/26513

Abstract: An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer. An electronic device has an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A white space region adjacent the electronic device includes a first P-type region in the semiconductor layer and adjacent the surface. The P-type region has a first sheet resistance and the NWELL region has a second sheet resistance that is greater than the first sheet resistance.

公开(公告)号：US20230129461A1

公开(公告)日：2023-04-27

申请号：US17512194

申请日：2021-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Honglin Guo ,  Thomas D. Bonifield

IPC: H01L49/02 ,  H01L25/16 ,  H01L23/31

Abstract: An integrated circuit includes a first isolation capacitor and a second isolation capacitor. The first isolation capacitor is electrically connected to a first circuit node and has first and second capacitor plates separated by a first dielectric stack. The second isolation capacitor is electrically connected in series between the first isolation capacitor and a second circuit node, and includes third and fourth capacitor plates separated by a second dielectric stack different from the first dielectric stack.

公开(公告)号：US11069627B2

公开(公告)日：2021-07-20

申请号：US14854896

申请日：2015-09-15

Applicant: Texas Instruments Incorporated

Inventor： Thomas D. Bonifield ,  Jeffrey A. West ,  Byron Williams ,  Honglin Guo

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/58 ,  H01L23/31 ,  H01L23/62

Abstract: A semiconductor die includes a plurality of layers, the plurality of layers having a top surface. A scribe seal is located in the plurality of layers and includes a first metal stack having a first metal layer located proximate the top surface. A trench is located in at least one layer of the plurality of layers. The trench extends from the top surface of the plurality of layers and is located a distance from the first metal stack. An electrical insulating layer is located on the top surface. The electrical insulating layer covers at least a portion of the top surface adjacent the first metal layer and extends a distance from the top surface of the first metal layer.

公开(公告)号：US09793106B2

公开(公告)日：2017-10-17

申请号：US14931822

申请日：2015-11-03

Applicant: Texas Instruments Incorporated

Inventor： Honglin Guo ,  Tim A. Taylor ,  Jeff A. West ,  Ricky A. Jackson ,  Byron Williams

IPC: H01L49/02 ,  H01G4/14 ,  H01L21/02 ,  H01G4/224 ,  H01L51/00 ,  H01G4/18 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/02118 ,  H01G4/14 ,  H01G4/18 ,  H01G4/224 ,  H01G4/236 ,  H01G4/33 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/0228 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/564 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L28/40 ,  H01L51/00 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/04042 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/45099

Abstract: It has been discovered that poor TDDB reliability of microelectronic device capacitors with organic polymer material in the capacitor dielectric is due to water molecules infiltrating the organic polymer material when the microelectronic device is exposed to water vapor in the operating ambient. Water molecule infiltration from water vapor in the ambient is effectively reduced by a moisture barrier comprising a layer of aluminum oxide formed by an atomic layer deposition (ALD) process. A microelectronic device includes a capacitor with organic polymer material in the capacitor dielectric and a moisture barrier with a layer of aluminum oxide formed by an ALD process.

公开(公告)号：US12046602B2

公开(公告)日：2024-07-23

申请号：US17665501

申请日：2022-02-05

Applicant: Texas Instruments Incorporated

Inventor： Honglin Guo ,  Frank John Sweeney

IPC: H01L27/12 ,  H01L21/265 ,  H01L23/00 ,  H01L29/94 ,  H01L33/64

CPC classification number: H01L27/1203 ,  H01L23/564 ,  H01L21/26513 ,  H01L29/94 ,  H01L33/645

Abstract: An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer. An electronic device has an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A white space region adjacent the electronic device includes a first P-type region in the semiconductor layer and adjacent the surface. The P-type region has a first sheet resistance and the NWELL region has a second sheet resistance that is greater than the first sheet resistance.

公开(公告)号：US20230307557A1

公开(公告)日：2023-09-28

申请号：US17665497

申请日：2022-02-05

Applicant: Texas Instruments Incorporated

Inventor： Honglin Guo ,  Zachary K Lee ,  Jingjing Chen

IPC: H01L29/94 ,  H01L29/66

CPC classification number: H01L29/94 ,  H01L29/66189 ,  H01L21/26513

Abstract: An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer; the semiconductor layer contains white space regions that include a PWELL region. An electronic device includes an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A sacrificial NWELL ring is adjacent to and separated from the NWELL region by a first gap.

公开(公告)号：US11424183B2

公开(公告)日：2022-08-23

申请号：US16995288

申请日：2020-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Qi-Zhong Hong ,  Honglin Guo ,  Benjamin James Timmer ,  Gregory Boyd Shinn

IPC: H01L23/522 ,  H01L49/02

Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.