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    Processing device with a microbranch target buffer for branch prediction using loop iteration count
    11.
    发明授权
    Processing device with a microbranch target buffer for branch prediction using loop iteration count 有权

    公开(公告)号：US11294681B2

    公开(公告)日：2022-04-05

    申请号：US16888783

    申请日：2020-05-31

    Applicant: Texas Instruments Incorporated

    Inventor： Kai Chirca ,  Paul Daniel Gauvreau ,  David Edward Smith, Jr.

    IPC: G06F9/32 ,  G06F9/38

    Abstract: An integrated circuit comprising instruction processing circuitry for processing a plurality of program instructions and instruction prediction circuitry. The instruction prediction circuitry comprises circuitry for detecting successive occurrences of a same program loop sequence of program instructions. The instruction prediction circuitry also comprises circuitry for predicting a number of iterations of the same program loop sequence of program instructions, in response to detecting, by the circuitry for detecting, that a second occurrence of the same program loop sequence of program instructions comprises a same number of iterations as a first occurrence of the same program loop sequence of program instructions.

    MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
    13.
    发明申请
    MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM 有权

    公开(公告)号：US20220027275A1

    公开(公告)日：2022-01-27

    申请号：US17492776

    申请日：2021-10-04

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  Kai Chirca ,  David Matthew Thompson

    IPC: G06F12/0842 ,  G06F12/0811 ,  G06F12/0888 ,  G06F1/14 ,  G06F9/54

    Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

    Memory pipeline control in a hierarchical memory system
    14.
    发明授权
    Memory pipeline control in a hierarchical memory system 有权

    公开(公告)号：US11138117B2

    公开(公告)日：2021-10-05

    申请号：US16879264

    申请日：2020-05-20

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  Kai Chirca ,  David Matthew Thompson

    IPC: G06F12/00 ,  G06F12/0842 ,  G06F12/0811 ,  G06F12/0888 ,  G06F1/14 ,  G06F9/54

    Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

    STREAMING ENGINE WITH DEFERRED EXCEPTION REPORTING
    18.
    发明申请
    STREAMING ENGINE WITH DEFERRED EXCEPTION REPORTING 审中-公开

    公开(公告)号：US20180365122A1

    公开(公告)日：2018-12-20

    申请号：US16112996

    申请日：2018-08-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Joseph Zbiciak ,  Timothy D. Anderson ,  Duc Bui ,  Kai Chirca

    IPC: G06F11/30 ,  G06F13/16 ,  G06F11/00 ,  G06F12/0875 ,  G06F11/27 ,  G06F12/0862 ,  G06F9/38 ,  G06F9/30 ,  G06F9/345

    Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.

    RECONFIGURABLE MATRIX MULTIPLIER SYSTEM AND METHOD
    19.
    发明申请
    RECONFIGURABLE MATRIX MULTIPLIER SYSTEM AND METHOD 审中-公开

    公开(公告)号：US20180246855A1

    公开(公告)日：2018-08-30

    申请号：US15905250

    申请日：2018-02-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Arthur John Redfern ,  Donald Edward Steiss ,  Timothy David Anderson ,  Kai Chirca

    IPC: G06F17/16

    Abstract: A reconfigurable matrix multiplier (RMM) system/method allowing tight or loose coupling to supervisory control processor application control logic (ACL) in a system-on-a-chip (SOC) environment is disclosed. The RMM provides for C=A*B matrix multiplication operations having A-multiplier-matrix (AMM), B-multiplicand-matrix (BMM), and C-product-matrix (CPM), as well as C=A*B+D operations in which D-summation-matrix (DSM) represents the result of a previous multiplication operation or another previously defined matrix. The RMM provides for additional CPM LOAD/STORE paths allowing overlapping of compute/data transfer operations and provides for CPM data feedback to the AMM or BMM operand inputs from a previously calculated CPM result. The RMM anticipates the use of 8, 16, and 32-bit operand reconfigurable matrix datum in conjunction with a typical external memory bus data width of 512 bits and an instruction control unit (ICU) implemented using a series of RMM configuration words (RCW) and streaming opcode functions (SOF).

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