公开(公告)号：US20170222040A1

公开(公告)日：2017-08-03

申请号：US15485892

申请日：2017-04-12

Applicant: Texas Instruments Incorporated

Inventor： Marie DENISON ,  Sameer PENDHARKAR ,  Guru MATHUR

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/06 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/823487 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/51 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66734 ,  H01L29/7809

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

公开(公告)号：US20150171212A1

公开(公告)日：2015-06-18

申请号：US14567196

申请日：2014-12-11

Applicant: Texas Instruments Incorporated

Inventor： Philip Leland HOWER ,  Sameer PENDHARKAR ,  Marie DENISON

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L27/088 ,  H01L21/266 ,  H01L21/324 ,  H01L21/225 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/66681 ,  H01L21/2253 ,  H01L21/266 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0642 ,  H01L29/0646 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.

Abstract translation: 一种集成电路和方法，其具有具有埋入漂移区域的扩展漏极MOS晶体管，漏极扩散链路，沟道扩散链路和电隔离源极的隔离链路，其中通过分割区域注入形成隔离扩散链路 将掺杂稀释到漏极扩散链路中的掺杂的三分之二以下。

公开(公告)号：US20150097231A1

公开(公告)日：2015-04-09

申请号：US14044926

申请日：2013-10-03

Applicant: Texas Instruments Incorporated

Inventor： Guru MATHUR ,  Marie DENISON ,  Sameer PENDHARKAR

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/063 ,  H01L21/266 ,  H01L21/76232 ,  H01L21/823418 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift region bounded on at least two opposite sides by the deep trench structures. The deep trench structures include dielectric liners. The deep trench structures are spaced so as to form RESURF regions for the drift region. Vertical gates are formed in vertically oriented gate trenches in the dielectric liners of the deep trench structures, abutting the vertical drift regions. A body implant mask for implanting dopants for the transistor body is also used as an etch mask for forming the vertically oriented gate trenches in the dielectric liners.

公开(公告)号：US20200381552A1

公开(公告)日：2020-12-03

申请号：US16995133

申请日：2020-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Marie DENISON ,  Sameer PENDHARKAR ,  Guru MATHUR

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L29/51

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

公开(公告)号：US20200146945A1

公开(公告)日：2020-05-14

申请号：US16735729

申请日：2020-01-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Marie DENISON ,  Philip L. HOWER ,  Sameer PENDHARKAR

IPC: A61J17/00 ,  A61B90/70

Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.

公开(公告)号：US20170125513A1

公开(公告)日：2017-05-04

申请号：US15403403

申请日：2017-01-11

Applicant: Texas Instruments Incorporated

Inventor： Marie DENISON ,  Sameer PENDHARKAR ,  Guru MATHUR

IPC: H01L29/06 ,  H01L21/283 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L21/225 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/823487 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/51 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66734 ,  H01L29/7809

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

公开(公告)号：US20160071923A1

公开(公告)日：2016-03-10

申请号：US14944450

申请日：2015-11-18

Applicant: Texas Instruments Incorporated

Inventor： Marie DENISON ,  Sameer PENDHARKAR ,  Guru MATHUR

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L21/225 ,  H01L21/324 ,  H01L21/283 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/823487 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/51 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66734 ,  H01L29/7809

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

公开(公告)号：US20150325638A1

公开(公告)日：2015-11-12

申请号：US14807276

申请日：2015-07-23

Applicant: Texas Instruments Incorporated

Inventor： Guru MATHUR ,  Marie DENISON ,  Sameer PENDHARKAR

IPC: H01L29/06 ,  H01L21/266 ,  H01L29/10 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/063 ,  H01L21/266 ,  H01L21/76232 ,  H01L21/823418 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift region bounded on at least two opposite sides by the deep trench structures. The deep trench structures include dielectric liners. The deep trench structures are spaced so as to form RESURF regions for the drift region. Vertical gates are formed in vertically oriented gate trenches in the dielectric liners of the deep trench structures, abutting the vertical drift regions. A body implant mask for implanting dopants for the transistor body is also used as an etch mask for forming the vertically oriented gate trenches in the dielectric liners.

Abstract translation: 具有垂直漏极延伸MOS晶体管的半导体器件可以通过形成深沟槽结构来形成，以限定由深沟槽结构限定在至少两个相对侧上的至少一个垂直漂移区域。 深沟槽结构包括电介质衬垫。 深沟槽结构被间隔开以形成漂移区域的RESURF区域。 垂直栅极形成在深沟槽结构的电介质衬里中的垂直取向的栅极沟槽中，邻接垂直漂移区。 用于注入用于晶体管本体的掺杂剂的物体注入掩模也用作用于在电介质衬垫中形成垂直取向的栅极沟槽的蚀刻掩模。

公开(公告)号：US20150171213A1

公开(公告)日：2015-06-18

申请号：US14567398

申请日：2014-12-11

Applicant: Texas Instruments Incorporated

Inventor： Philip Leland HOWER ,  Sameer PENDHARKAR ,  Marie DENISON

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/105

CPC classification number: H01L29/7816 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.

Abstract translation: 一种集成电路和方法，其具有具有埋入漂移区域的扩展漏极MOS晶体管，在埋入漂移区域和漏极接触之间的漏极扩散连接，以及在埋入漂移区域和沟道之间同时形成的通道端扩散连接，其中 沟道末端扩散链路是通过分段区域注入形成的，以将掺杂稀释到漏极端扩散链路中的掺杂量的不到三分之二。

公开(公告)号：US20150097225A1

公开(公告)日：2015-04-09

申请号：US14044909

申请日：2013-10-03

Applicant: Texas Instruments Incorporated

Inventor： Marie DENISON ,  Sameer PENDHARKAR ,  Guru MATHUR

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/66712 ,  H01L21/225 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/42368 ,  H01L29/66674 ,  H01L29/66734 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7813

Abstract: A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the vertical drift region by at least one instance of the deep trench structures. Dopants are implanted into the vertical drain contact regions and the semiconductor device is annealed so that the implanted dopants diffuse proximate to a bottom of the deep trench structures. The vertical drain contact regions make electrical contact to the proximate vertical drift region at the bottom of the intervening deep trench structure. At least one gate, body region and source region are formed above the drift region at, or proximate to, a top surface of a substrate of the semiconductor device. The deep trench structures are spaced so as to form RESURF regions for the drift region.

Abstract translation: 半导体器件具有深沟槽结构的垂直漏极扩展MOS晶体管，以限定垂直漂移区域和至少一个垂直漏极接触区域，其通过深沟槽结构的至少一个实例与垂直漂移区域分离。 将掺杂剂注入到垂直漏极接触区域中，并且半导体器件被退火，使得注入的掺杂剂在深沟槽结构的底部附近扩散。 垂直漏极接触区域在中间深沟槽结构的底部处与邻近的垂直漂移区域电接触。 至少一个栅极，主体区域和源极区域形成在半导体器件的衬底的顶表面处或附近的漂移区域上方。 深沟槽结构被间隔开以形成漂移区域的RESURF区域。