公开(公告)号：US10423413B2

公开(公告)日：2019-09-24

申请号：US14326943

申请日：2014-07-09

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Peter Richard Dent

IPC: G06F9/30

Abstract: A method of loading and duplicating scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern.

公开(公告)号：US20240419606A1

公开(公告)日：2024-12-19

申请号：US18812008

申请日：2024-08-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Mujibur Rahman ,  Dheera Balasubramanian Samudrala ,  Peter Richard Dent ,  Duc Quang Bui

IPC: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F15/78 ,  G06F17/16 ,  H03H17/06

Abstract: An example device includes a first register storing a first vector comprised of a set of vector elements; a second register having a set of lanes and configured to store a second vector; and a storage that stores a set of control elements. Each such control element corresponds to a respective one of the vector elements of the set of vector elements in the first register. In addition, each control element of the set of control elements has a first portion that specifies, for the corresponding vector element of the set of vector elements, a lane of the set of lanes of the second register, and a second portion that specifies whether the corresponding vector element of the set of vector elements is to be routed to the lane specified by the first portion. The example device further includes processing circuitry to, based on an instruction that specifies the first register and the second register, generate the second vector based on the set of control elements.

公开(公告)号：US12105635B2

公开(公告)日：2024-10-01

申请号：US17384858

申请日：2021-07-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Mujibur Rahman ,  Dheera Balasubramanian Samudrala ,  Peter Richard Dent ,  Duc Quang Bui

IPC: G06F9/30 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1045 ,  G06F17/16 ,  H03H17/06 ,  G06F15/78

CPC classification number: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3856 ,  G06F9/3867 ,  G06F9/3887 ,  G06F9/48 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/0664 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3822 ,  G06F11/10 ,  G06F15/7807 ,  G06F15/781 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

Abstract: A method is provided that includes performing, by a processor in response to a vector permutation instruction, permutation of values stored in lanes of a vector to generate a permuted vector, wherein the permutation is responsive to a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane of the permuted vector indicates a value to be stored in the lane of the permuted vector, wherein the permute control input for at least one lane of the permuted vector indicates a value of a selected lane of the vector is to be stored in the at least one lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.

公开(公告)号：US20240320004A1

公开(公告)日：2024-09-26

申请号：US18670855

申请日：2024-05-22

Applicant: Texas Instruments Incorporated

Inventor： Duc Bui ,  Peter Richard Dent ,  Timothy D. Anderson

IPC: G06F9/30

CPC classification number: G06F9/3013 ,  G06F9/30036 ,  G06F9/30105

Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.

公开(公告)号：US12032961B2

公开(公告)日：2024-07-09

申请号：US18191066

申请日：2023-03-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Bui ,  Peter Richard Dent ,  Timothy D. Anderson

IPC: G06F9/30

CPC classification number: G06F9/3013 ,  G06F9/30036 ,  G06F9/30105

Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.

公开(公告)号：US20230367598A1

公开(公告)日：2023-11-16

申请号：US18191066

申请日：2023-03-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Bui ,  Peter Richard Dent ,  Timothy D. Anderson

IPC: G06F9/30

CPC classification number: G06F9/3013 ,  G06F9/30105 ,  G06F9/30036

Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.

公开(公告)号：US20210216313A1

公开(公告)日：2021-07-15

申请号：US17215013

申请日：2021-03-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Bui ,  Peter Richard Dent ,  Timothy D. Anderson

IPC: G06F9/30

Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.

公开(公告)号：US20150019838A1

公开(公告)日：2015-01-15

申请号：US14326943

申请日：2014-07-09

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Peter Richard Dent

IPC: G06F9/38 ,  G06F15/80 ,  G06F9/30

Abstract: A method of loading and duplicating scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern.

Abstract translation: 将标量数据从源加载和复制到目标寄存器的方法。 根据复制模式，数据可以以字节，半字，字或双字部分复制。