公开(公告)号：US10372531B2

公开(公告)日：2019-08-06

申请号：US15653749

申请日：2017-07-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Indu Prathapan ,  Prashanth Saraf ,  Desmond Pravin Martin Fernandes ,  Saket Jalan

IPC: G06F11/10 ,  G11C5/04 ,  G06F3/06 ,  G11C11/16 ,  G11C11/56 ,  H03M13/35 ,  G11C7/10 ,  G11C7/22

Abstract: In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.

公开(公告)号：US10331826B2

公开(公告)日：2019-06-25

申请号：US15630394

申请日：2017-06-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Wilson Pradeep ,  Prakash Narayanan ,  Saket Jalan

IPC: G06F17/50 ,  G06G7/62 ,  H03K19/00 ,  H01L23/58 ,  G01R31/28 ,  H01L29/10 ,  H01L25/00 ,  G01R27/28 ,  G01R31/36

Abstract: A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.

公开(公告)号：US20220283899A1

公开(公告)日：2022-09-08

申请号：US17824605

申请日：2022-05-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Indu Prathapan ,  Abhishek Ganapati Karkisaval

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.

公开(公告)号：US11194944B2

公开(公告)日：2021-12-07

申请号：US16989931

申请日：2020-08-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Wilson Pradeep ,  Prakash Narayanan ,  Saket Jalan

IPC: G06F30/3312 ,  G06F30/30 ,  G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  G01R31/28 ,  G01R27/28 ,  G01R31/36 ,  H03K19/00 ,  H01L29/10 ,  H01L25/00 ,  G06G7/62 ,  H01L23/58

Abstract: A method that includes disabling circuit paths in a circuit under test during transition fault testing (TFT) of valid timing paths of the circuit under test. The method then tests the circuit paths at slower clock speeds than the clock speed of the valid timing paths during TFT of the circuit paths. Finally, the method tests the circuit paths and the valid timing paths to facilitate testing of the circuit under test.

公开(公告)号：US20190317855A1

公开(公告)日：2019-10-17

申请号：US16453081

申请日：2019-06-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Indu Prathapan ,  Prashanth Saraf ,  Desmond Pravin Martin Fernandes ,  Saket Jalan

IPC: G06F11/10 ,  G06F3/06 ,  G11C11/56 ,  G11C11/16 ,  G11C5/04 ,  H03M13/37 ,  H03M13/35 ,  H03M13/19 ,  G11C7/22 ,  G11C7/10

Abstract: In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.

公开(公告)号：US20180252771A1

公开(公告)日：2018-09-06

申请号：US15973257

申请日：2018-05-07

Applicant: Texas Instruments Incorporated

Inventor： Sundarrajan Rangachari ,  Saket Jalan

IPC: G01R31/319 ,  G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/31901 ,  G01R31/31701 ,  G01R31/31703 ,  G01R31/31724 ,  G01R31/31727 ,  G01R31/3177

Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.

公开(公告)号：US20180107541A1

公开(公告)日：2018-04-19

申请号：US15844259

申请日：2017-12-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Indu Prathapan ,  Abishek Ganapati Karkisaval

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.

公开(公告)号：US20180059180A1

公开(公告)日：2018-03-01

申请号：US15255044

申请日：2016-09-01

Applicant: Texas Instruments Incorporated

Inventor： Sundarrajan Rangachari ,  Saket Jalan

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31901 ,  G01R31/31701 ,  G01R31/31703 ,  G01R31/31724 ,  G01R31/31727 ,  G01R31/3177

Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.

公开(公告)号：US20160170640A1

公开(公告)日：2016-06-16

申请号：US14571898

申请日：2014-12-16

Applicant: Texas Instruments Incorporated

Inventor： Saket Jalan ,  Rakesh Channabasappa Yaraduyathinahalli

IPC: G06F3/06

CPC classification number: G06F9/30141 ,  G11C7/1009 ,  H03K3/037

Abstract: The present invention is drawn to a register writing mechanism that does not require reading of the data in the register. In accordance with aspects of the present invention, each register is masked with a making bit provided by a masking component. In a first implementation, the first half of the bit registers are masked using data in the second half of the bit registers. In a second implementation, all the bit registers are masked using a masking word generated by the masking component.

Abstract translation: 本发明涉及一种不需要读取寄存器中的数据的寄存器写入机制。 根据本发明的方面，每个寄存器被掩蔽组件提供的制作位掩码。 在第一个实现中，使用位寄存器的后半部分的数据对位寄存器的前半部分进行掩码。 在第二实施例中，使用由掩蔽组件产生的屏蔽字来掩蔽所有位寄存器。

公开(公告)号：US11740968B2

公开(公告)日：2023-08-29

申请号：US17824605

申请日：2022-05-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Indu Prathapan ,  Abhishek Ganapati Karkisaval

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/064 ,  G06F3/0619 ,  G06F3/0673 ,  G06F11/1012 ,  G06F11/1048 ,  G11C29/52

Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.