公开(公告)号：US10186576B2

公开(公告)日：2019-01-22

申请号：US15714682

申请日：2017-09-25

Applicant: Texas Instruments Incorporated

Inventor： Raja Selvaraj ,  Anant Shankar Kamath ,  Byron Lovell Williams ,  Thomas D. Bonifield ,  John Kenneth Arch

IPC: H01L29/06 ,  H01L21/76 ,  H01L23/522 ,  H01L27/06 ,  H01L49/02 ,  H01L21/761 ,  H01L21/265 ,  H01L23/528 ,  H01L23/00

Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include methods of forming an integrated circuit including an isolator structure. The isolator structure includes parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator

公开(公告)号：US09806148B2

公开(公告)日：2017-10-31

申请号：US14680211

申请日：2015-04-07

Applicant: Texas Instruments Incorporated

Inventor： Raja Selvaraj ,  Anant Shankar Kamath ,  Byron Lovell Williams ,  Thomas D. Bonifield ,  John Kenneth Arch

IPC: H01L29/06 ,  H01L27/06 ,  H01L21/761 ,  H01L49/02 ,  H01L21/265 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L29/0646 ,  H01L21/265 ,  H01L21/761 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5286 ,  H01L24/05 ,  H01L27/0676 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/48463

Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

公开(公告)号：US20170309702A1

公开(公告)日：2017-10-26

申请号：US15646465

申请日：2017-07-11

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/552 ,  H01L23/642 ,  H01L28/40 ,  H01L2224/48463 ,  H01L2224/49107

Abstract: High voltage integrated circuit capacitors are disclosed. In an example arrangement, A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.

公开(公告)号：US20170062552A1

公开(公告)日：2017-03-02

申请号：US15348698

申请日：2016-11-10

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/552 ,  H01L23/642 ,  H01L28/40

Abstract: High voltage integrated circuit capacitors are disclosed. In an example arrangement. A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.

Abstract translation: 公开了高压集成电路电容器。 在一个例子中。 电容器结构包括半导体衬底; 底板，其具有覆盖在半导体衬底上的导电层; 沉积在所述底板的至少一部分上并且在第一区域中具有大于约6um的第一厚度的电容器电介质层; 在第一区域的边缘处的电容器电介质中的倾斜过渡区域，所述倾斜过渡区域具有从水平面倾斜大于5度的上表面，并且从第一区域延伸到电容器电介质的第二区域 层，其具有比第一厚度低的第二厚度; 以及形成在所述第一区域中覆盖所述电容器电介质层的至少一部分的顶板导体。 公开了方法和附加装置布置。

公开(公告)号：US20160379953A1

公开(公告)日：2016-12-29

申请号：US14749219

申请日：2015-06-24

Applicant: Texas Instruments Incorporated

Inventor： Patrick Francis Thompson ,  Jeffrey Alan West ,  Thomas D. Bonifield ,  Fu-Kang Hsu ,  Ching-Lun Hsia

IPC: H01L23/00

CPC classification number: H01L24/48 ,  H01L23/642 ,  H01L24/03 ,  H01L24/05 ,  H01L24/85 ,  H01L2224/03462 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/4554 ,  H01L2924/00015 ,  H01L2224/29099

Abstract: Circuitry is disclosed that includes a first conductive portion of a first die and a first conductive pillar electrically and physically connected to the first conductive portion. The first conductive pillar includes a first conductive pillar surface. A first bond connects the first conductive pillar surface to a first end of a bond wire.

Abstract translation: 公开了包括第一管芯的第一导电部分和与第一导电部分物理电连接的第一导电柱的电路。 第一导电柱包括第一导电柱表面。 第一接合将第一导电柱表面连接到接合线的第一端。

公开(公告)号：US09299697B2

公开(公告)日：2016-03-29

申请号：US14277851

申请日：2014-05-15

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L27/06 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L49/02 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L28/91 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823481 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0692 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7833

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

Abstract translation: 微电子器件包含具有高电压节点和低电压节点的高电压分量。 高电压节点通过微电子器件的基板的表面处的高压节点和低电压元件之间的主电介质与低电压节点隔离。 低压隙电介质层设置在高电压节点和主电介质之间。 低带隙电介质层含有至少一个带隙能量小于主电介质带隙能量的子层。 低带隙电介质层围绕高压节点连续延伸超过高压节点。 较低带隙电介质层具有围绕高电压节点的隔离断裂，距离高压节点的至少两倍于低带隙电介质层的厚度。

公开(公告)号：US20230129461A1

公开(公告)日：2023-04-27

申请号：US17512194

申请日：2021-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Honglin Guo ,  Thomas D. Bonifield

IPC: H01L49/02 ,  H01L25/16 ,  H01L23/31

Abstract: An integrated circuit includes a first isolation capacitor and a second isolation capacitor. The first isolation capacitor is electrically connected to a first circuit node and has first and second capacitor plates separated by a first dielectric stack. The second isolation capacitor is electrically connected in series between the first isolation capacitor and a second circuit node, and includes third and fourth capacitor plates separated by a second dielectric stack different from the first dielectric stack.

公开(公告)号：US11087451B2

公开(公告)日：2021-08-10

申请号：US15847600

申请日：2017-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Elizabeth C. Stewart ,  Young Sawk Oh ,  Zhiyi Yu ,  Jeffrey A. West ,  Thomas D. Bonifield

IPC: G06K9/00 ,  G06T7/00

Abstract: A method comprises obtaining a wafer comprising a plurality of components, wherein each of the plurality of components exposes a first surface of the component present in a first focal plane and a second surface of the component present in a second focal plane. The method comprises generating, by an optical tool, a first image of the first surface and a second image of the second surface of one of the plurality of components. The method comprises comparing, by a processor, the first image with a first reference image to produce a first value and the second image with a second reference image to produce a second value. The method comprises generating, by the processor, a wafer map indicating a quality state of the one of the plurality of components based on the first and second values.

公开(公告)号：US11069627B2

公开(公告)日：2021-07-20

申请号：US14854896

申请日：2015-09-15

Applicant: Texas Instruments Incorporated

Inventor： Thomas D. Bonifield ,  Jeffrey A. West ,  Byron Williams ,  Honglin Guo

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/58 ,  H01L23/31 ,  H01L23/62

Abstract: A semiconductor die includes a plurality of layers, the plurality of layers having a top surface. A scribe seal is located in the plurality of layers and includes a first metal stack having a first metal layer located proximate the top surface. A trench is located in at least one layer of the plurality of layers. The trench extends from the top surface of the plurality of layers and is located a distance from the first metal stack. An electrical insulating layer is located on the top surface. The electrical insulating layer covers at least a portion of the top surface adjacent the first metal layer and extends a distance from the top surface of the first metal layer.

公开(公告)号：US10707297B2

公开(公告)日：2020-07-07

申请号：US16178065

申请日：2018-11-01

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L49/02 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L23/522 ,  H01L27/06

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.