公开(公告)号：US09479186B1

公开(公告)日：2016-10-25

申请号：US14871373

申请日：2015-09-30

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy Naru ,  Nagarajan Viswanathan ,  Visvesvaraya Pentakota

IPC: H03M1/12 ,  H03M1/06 ,  H03M1/00 ,  H03M1/36

CPC classification number: H03M1/0609 ,  H03M1/203 ,  H03M1/361

Abstract: In described examples, an analog to digital converter (ADC) includes a main ADC and a reference ADC. The main ADC generates a zone information signal and a digital output in response to an input signal. The reference ADC receives a plurality of reference voltages from the main ADC. The plurality of reference voltages includes a first reference voltage and a second reference voltage. The reference ADC generates a reference output in response to the input signal, the first reference voltage and the second reference voltage. A subtractor generates an error signal in response to the digital output and the reference output. A logic block generates one of a first offset correction signal, a second offset correction signal and a gain mismatch signal in response to the zone information signal, the error signal and the reference output.

Abstract translation: 在所描述的示例中，模数转换器（ADC）包括主ADC和参考ADC。 主ADC响应于输入信号产生区域信息信号和数字输出。 参考ADC从主ADC接收多个参考电压。 多个参考电压包括第一参考电压和第二参考电压。 参考ADC根据输入信号，第一参考电压和第二参考电压产生参考输出。 减法器响应于数字输出和参考输出产生一个误差信号。 响应于区域信息信号，误差信号和参考输出，逻辑块产生第一偏移校正信号，第二偏移校正信号和增益失配信号中的一个。

公开(公告)号：US20130294295A1

公开(公告)日：2013-11-07

申请号：US13872093

申请日：2013-04-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nagarajan Viswanathan ,  Visvesvaraya Pentakota ,  Robert Clair Keller ,  Thomas Neu ,  Francesco Dantoni

IPC: H04L5/14

CPC classification number: H04L5/1461 ,  H04B1/525

Abstract: Apparatus and methods disclosed herein implement an RF receive-band filter at a receive chain input of a wireless base station with a co-located transmitter and receiver. The RF receive-band filter includes an adaptive filter component to perform filtering operations on samples of a digital baseband or intermediate frequency signal x(n) from a transmit chain associated with the wireless base station. An adaptive filter transfer function is determined in real time such that samples of the baseband transmit signal x(n) are transformed into a cancellation baseband signal z(n). The digital cancelation baseband signal z(n) is then digital-to-analog converted and the resulting analog baseband signal z(t) is up-converted to obtain a subtractive RF cancelation signal c(t). C(t) is summed with a desirable received signal RF component r(t) and an undesirable transmitter leakage RF signal component l(t) appearing at the input to the base station receiver. C(t) cancels l(t), leaving r(t) to be processed by the receiver section of the base station.

Abstract translation: 本文公开的装置和方法在具有共位发射器和接收器的无线基站的接收链输入端实现RF接收带滤波器。 RF接收带滤波器包括自适应滤波器组件，用于对与无线基站相关联的发射链进行数字基带或中频信号x（n）的采样执行滤波操作。 实时地确定自适应滤波器传递函数，使得基带发送信号x（n）的采样被变换为消除基带信号z（n）。 然后对数字消除基带信号z（n）进行数模转换，并将所得到的模拟基带信号z（t）上变频以获得减法RF消除信号c（t）。 C（t）与期望的接收信号RF分量r（t）和出现在基站接收机的输入处的不期望的发射机泄漏RF信号分量l（t）相加。 C（t）取消l（t），使r（t）由基站的接收机部分处理。

公开(公告)号：US10693444B1

公开(公告)日：2020-06-23

申请号：US16396873

申请日：2019-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nagalinga Swamy Basayya Aremallapur ,  Eeshan Miglani ,  Visvesvaraya Pentakota ,  Praxal Sunilkumar Shah

IPC: H03K3/013 ,  H03K3/037 ,  H03K21/10

Abstract: A spur cancellation circuit for use in a mixed signal circuit. A spur cancellation circuit includes a clock generation circuit, a flip-flop bank, and a control circuit. The clock generation circuit is configured to generate a clock signal. The flip-flop bank is coupled to the clock generation circuit, and includes a plurality of flip-flops configured to be clocked by the clock signal. The control circuit is coupled to the clock generation circuit and the flip-flop bank. The control circuit is configured to individually enable one or more of the flip-flops to change state responsive to the clock signal and consume a predetermined amount of power; and to provide a data value to be clocked into the flip-flops.

公开(公告)号：US20180183409A1

公开(公告)日：2018-06-28

申请号：US15852237

申请日：2017-12-22

Applicant: Texas Instruments Incorporated

Inventor： Rajendrakumar Joish ,  Visvesvaraya Pentakota

IPC: H03H11/24 ,  H03H7/25 ,  H03G1/00 ,  H03K17/687 ,  H01F38/14

CPC classification number: H03H11/245 ,  H01F38/14 ,  H03G1/0088 ,  H03G3/001 ,  H03G3/3052 ,  H03G2201/106 ,  H03H7/25 ,  H03K17/687 ,  H04B1/18

Abstract: The disclosure provides an RF receiver. The RF receiver includes an input driver. The input driver receives a coarse signal, and generates an input signal. A digital step attenuator (DSA) is coupled to the input driver and receives the input signal. An analog to digital converter (ADC) is coupled to the DSA. The DSA includes a serial capacitor coupled to the input driver. The DSA also includes a sampling capacitor coupled to the ADC.

公开(公告)号：US09001712B2

公开(公告)日：2015-04-07

申请号：US13872093

申请日：2013-04-27

Applicant: Texas Instruments Incorporated

Inventor： Nagarajan Viswanathan ,  Visvesvaraya Pentakota ,  Robert Clair Keller ,  Thomas Neu ,  Francesco Dantoni

IPC: H04B1/52 ,  H04L5/14

CPC classification number: H04L5/1461 ,  H04B1/525

Abstract: Apparatus and methods disclosed herein implement an RF receive-band filter at a receive chain input of a wireless base station with a co-located transmitter and receiver. The RF receive-band filter includes an adaptive filter component to perform filtering operations on samples of a digital baseband or intermediate frequency signal x(n) from a transmit chain associated with the wireless base station. An adaptive filter transfer function is determined in real time such that samples of the baseband transmit signal x(n) are transformed into a cancellation baseband signal z(n). The digital cancelation baseband signal z(n) is then digital-to-analog converted and the resulting analog baseband signal z(t) is up-converted to obtain a subtractive RF cancelation signal c(t). C(t) is summed with a desirable received signal RF component r(t) and an undesirable transmitter leakage RF signal component l(t) appearing at the input to the base station receiver. C(t) cancels l(t), leaving r(t) to be processed by the receiver section of the base station.

Abstract translation: 本文公开的装置和方法在具有共位发射器和接收器的无线基站的接收链输入端实现RF接收带滤波器。 RF接收带滤波器包括自适应滤波器组件，用于对与无线基站相关联的发射链进行数字基带或中频信号x（n）的采样执行滤波操作。 实时地确定自适应滤波器传递函数，使得基带发送信号x（n）的采样被变换为消除基带信号z（n）。 然后对数字消除基带信号z（n）进行数模转换，并将所得到的模拟基带信号z（t）上变频以获得减法RF消除信号c（t）。 C（t）与期望的接收信号RF分量r（t）和出现在基站接收机的输入处的不期望的发射机泄漏RF信号分量l（t）相加。 C（t）取消l（t），使r（t）由基站的接收机部分处理。

公开(公告)号：US20250096813A1

公开(公告)日：2025-03-20

申请号：US18966610

申请日：2024-12-03

Applicant: Texas Instruments Incorporated

Inventor： Sai Aditya Nurani ,  Rishi Soundararajan ,  Nithin Gopinath ,  Visvesvaraya Pentakota ,  Shagun Dusad

IPC: H03M1/12 ,  H03M1/44 ,  H03M1/50 ,  H03M1/78

Abstract: An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.

公开(公告)号：US11533068B1

公开(公告)日：2022-12-20

申请号：US17462145

申请日：2021-08-31

Applicant: Texas Instruments Incorporated

Inventor： Rahul Sharma ,  Karthikeyan Gunasekaran ,  Sarma Sundareswara Gunturi ,  Ram Narayan Krishna Nama Mony ,  Jaiganesh Balakrishnan ,  Sandeep Kesrimal Oswal ,  Visvesvaraya Pentakota

IPC: H04L5/12 ,  H04L23/02 ,  H04B1/00 ,  H04B1/30

Abstract: A radio frequency transmitter includes an upconverter that outputs in-phase (I) and quadrature (Q) signals, a digital timing offset circuit, first and second digital-to-analog converters (DACs), an analog timing offset removal circuit, first and second pulse shapers, and an adder. The digital timing offset circuit introduces a time offset between the I and Q signals. The first and second DACs output analog I and Q signals, respectively, and have first and second clock signals, respectively. The first and second clock signals have the same frequency and are offset relative to each other by the time offset. The analog timing offset removal circuit removes the time offset between the analog I and Q signals. The first and second pulse shapers receive the analog I and Q signals, respectively, and output pulse-shaped I and Q signals. The adder receives the pulse-shaped I and Q signals and outputs an intermediate frequency signal.

公开(公告)号：US20200177288A1

公开(公告)日：2020-06-04

申请号：US16697236

申请日：2019-11-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sandeep Oswal ,  Visvesvaraya Pentakota ,  Jagannathan Venkataraman ,  Jaiganesh Balakrishnan ,  Francesco Dantoni

IPC: H04B17/13 ,  H04L27/36 ,  H04B1/04

Abstract: A transmitter for an RF communications system, that includes an auxiliary receiver for capturing transmit signal data for use in compensating/correcting transmit signal impairments (such as for DPD, QMC, LOL). The transmitter (such as Zero IF) includes analog chain elements that introduce transmit signal impairments (such as PA nonlinearities). The auxiliary receiver is configured to receive loopback transmit RF signals, and includes an RF direct sampling ADC to convert the loopback transmit RF signals to digital transmit RF signals. Digital down conversion circuitry is configured to downconvert the digital transmit RF signals to captured digital transmit baseband signals, and data capture circuitry is configured to generate the transmit signal data based on the captured digital transmit baseband signals.

公开(公告)号：US10284188B1

公开(公告)日：2019-05-07

申请号：US15945165

申请日：2018-04-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rishi Soundararajan ,  Visvesvaraya Pentakota

IPC: H03K5/24 ,  H03M1/50 ,  H03K5/00

Abstract: A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.

公开(公告)号：US09548752B1

公开(公告)日：2017-01-17

申请号：US15048027

申请日：2016-02-19

Applicant: Texas Instruments Incorporated

Inventor： Neeraj Shrivastava ,  Supreet Joshi ,  Himanshu Varshney ,  Jafar Sadique Kaviladath ,  Visvesvaraya Pentakota ,  Shagun Dusad

IPC: H03M1/66 ,  H03M1/10 ,  H03M1/78 ,  H03M1/74

CPC classification number: H03M1/1009 ,  H03M1/1019 ,  H03M1/1057 ,  H03M1/66 ,  H03M1/742 ,  H03M1/745 ,  H03M1/785

Abstract: The disclosure provides a current steering digital to analog converter (DAC) that includes a plurality of DAC elements. At least one DAC element of the plurality of DAC elements is coupled to a calibration circuit. The calibration circuit includes a fixed current source coupled to a primary node of the DAC element through a first estimation switch. A digital code generator is coupled to the primary node, and generates a first digital code corresponding to a primary voltage generated at the primary node. The digital code generator generates a second digital code. A correction DAC is coupled to the digital code generator and generates a bias voltage based on the second digital code. The bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal.

Abstract translation: 本公开提供了包括多个DAC元件的电流转向数模转换器（DAC）。 多个DAC元件中的至少一个DAC元件耦合到校准电路。 校准电路包括通过第一估计开关耦合到DAC元件的主节点的固定电流源。 数字码发生器耦合到主节点，并且产生对应于在主节点处产生的主电压的第一数字码。 数字代码生成器产生第二数字代码。 校正DAC耦合到数字代码发生器并且基于第二数字代码产生偏置电压。 偏置电压被提供给DAC元件，使得流过多个DAC元件中的每个DAC元件的电流相等。