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11.发明申请TECHNIQUE FOR THE GROWTH AND FABRICATION OF SEMIPOLAR (Ga,Al,In,B)N THIN FILMS, HETEROSTRUCTURES, AND DEVICES 审中-公开（Ga，Al，In，B）N薄膜，异质结构和器件的生长和制备技术公开(公告)号：US20140211820A1
公开(公告)日：2014-07-31
申请号：US14229674
申请日：2014-03-28
Applicant: The Regents of the University of California
Inventor： Robert M. Farrell, JR. , Troy J. Baker , Arpan Chakraborty , Benjamin A. Haskell , P. Morgan Pattison , Rajat Sharma , Umesh K. Mishra , Steven P. DenBaars , James S. Speck , Shuji Nakamura
IPC: H01S5/343
CPC classification number: H01L33/16 , B82Y20/00 , C30B23/025 , C30B25/18 , C30B29/403 , H01L21/02389 , H01L21/0242 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L21/02609 , H01L33/0004 , H01L33/0062 , H01L33/007 , H01L33/02 , H01S5/0422 , H01S5/2201 , H01S5/3202 , H01S5/34333 , H01S2304/04
Abstract: A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.
Abstract translation: 一种用于生长和制造半极性（Ga，Al，In，B）N薄膜，异质结构和器件的方法，包括鉴定特定器件应用的所需材料性质，基于所需材料性质选择半极性生长取向，选择 用于生长选择的半极性生长取向的合适底物，在衬底上生长平面半极性（Ga，Al，In，B）N模板或成核层，以及生长半极（Ga，Al，In，B）N薄膜 ，平面半极性（Ga，Al，In，B）N模板或成核层上的异质结构或器件。 该方法导致大面积的半极性（Ga，Al，In，B）N薄膜，异质结构和器件平行于衬底表面。
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公开(公告)号：US08796912B2
公开(公告)日：2014-08-05
申请号：US13622979
申请日：2012-09-19
Applicant: The Regents of the University of California
Inventor： Arpan Chakraborty , Likun Shen , Umesh K. Mishra
IPC: H01J1/62
CPC classification number: H01L25/0753 , F21K9/00 , H01L27/156 , H01L33/08 , H01L33/14 , H01L33/20 , H01L33/38 , H01L33/385 , H01L33/42 , H01L33/486 , H01L33/62 , H01L33/64 , H01L2924/0002 , H01L2933/0033 , H01L2933/0066 , H01L2924/00
Abstract: The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.
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Patent Agency Ranking
13.发明申请ANISOTROPIC STRAIN CONTROL IN SEMIPOLAR NITRIDE QUANTUM WELLS BY PARTIALLY OR FULLY RELAXED ALUMINUM INDIUM GALLIUM NITRIDE LAYERS WITH MISFIT DISLOCATIONS 有权通过部分或完全放松的铝氮化镓氮化物层与杂质分离的二氧化氮量子阱中的各向异性应变控制公开(公告)号：US20130259080A1
公开(公告)日：2013-10-03
申请号：US13904908
申请日：2013-05-29
Applicant: The Regents of the University of California
Inventor： Hiroaki Ohta , Feng Wu , Anurag Tyagi , Arpan Chakraborty , James S. Speck , Steven P. DenBaars , Shuji Nakamura , Erin C. Young
CPC classification number: H01S5/34333 , B82Y20/00 , H01L21/02389 , H01L21/0242 , H01L21/02433 , H01L21/0254 , H01L33/0075 , H01L33/12 , H01L33/16 , H01L33/32 , H01S5/2201 , H01S5/32 , H01S5/3201 , H01S5/3202 , H01S5/3403 , H01S5/3425 , H01S2301/173
Abstract: An epitaxial structure for a III-Nitride based optical device, comprising an active layer with anisotropic strain on an underlying layer, where a lattice constant and strain in the underlying layer are partially or fully relaxed in at least one direction due to a presence of misfit dislocations, so that the anisotropic strain in the active layer is modulated by the underlying layer.
Abstract translation: 用于基于III-Nitride的光学器件的外延结构，其包括在下层上具有各向异性应变的活性层，其中由于存在失配而使底层中的晶格常数和应变在至少一个方向上部分或完全松弛 位错，使得有源层中的各向异性应变被下层调制。
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14.发明授权Technique for the growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices 有权用于生长和制造半极性（Ga，Al，In，B）N薄膜，异质结构和器件的技术公开(公告)号：US09231376B2
公开(公告)日：2016-01-05
申请号：US14229674
申请日：2014-03-28
Applicant: The Regents of the University of California
Inventor： Robert M. Farrell, Jr. , Troy J. Baker , Arpan Chakraborty , Benjamin A. Haskell , P. Morgan Pattison , Rajat Sharma , Umesh K. Mishra , Steven P. DenBaars , James S. Speck , Shuji Nakamura
IPC: H01L33/30 , H01S5/343 , B82Y20/00 , C30B23/02 , C30B25/18 , C30B29/40 , H01L21/02 , H01L33/00 , H01S5/042 , H01S5/22 , H01S5/32
CPC classification number: H01L33/16 , B82Y20/00 , C30B23/025 , C30B25/18 , C30B29/403 , H01L21/02389 , H01L21/0242 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L21/02609 , H01L33/0004 , H01L33/0062 , H01L33/007 , H01L33/02 , H01S5/0422 , H01S5/2201 , H01S5/3202 , H01S5/34333 , H01S2304/04
Abstract: A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.
Abstract translation: 一种用于生长和制造半极性（Ga，Al，In，B）N薄膜，异质结构和器件的方法，包括鉴定特定器件应用的所需材料性质，基于所需材料性质选择半极性生长取向，选择 用于生长选择的半极性生长取向的合适底物，在衬底上生长平面半极性（Ga，Al，In，B）N模板或成核层，以及生长半极（Ga，Al，In，B）N薄膜 ，平面半极性（Ga，Al，In，B）N模板或成核层上的异质结构或器件。 该方法导致大面积的半极性（Ga，Al，In，B）N薄膜，异质结构和器件平行于衬底表面。
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公开(公告)号：US20150076533A1
公开(公告)日：2015-03-19
申请号：US14553625
申请日：2014-11-25
Applicant: The Regents of the University of California
Inventor： Arpan Chakraborty , Likun Shen , Umesh K. Mishra
CPC classification number: H01L25/0753 , F21K9/00 , H01L27/156 , H01L33/08 , H01L33/14 , H01L33/20 , H01L33/38 , H01L33/385 , H01L33/42 , H01L33/486 , H01L33/62 , H01L33/64 , H01L2924/0002 , H01L2933/0033 , H01L2933/0066 , H01L2924/00
Abstract: The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistance with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.
Abstract translation: 本发明公开了排列成阵列的多个叉指像素，具有非常低的串联电阻，具有改进的电流扩散和改善的散热。 每个像素是具有尺寸l的边的正方形。 通过增加像素的有源区域的周长来使串联电阻最小化。 串联电阻也通过缩小每个像素的台面和n接触之间的空间来最小化。
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公开(公告)号：US08922110B2
公开(公告)日：2014-12-30
申请号：US14311071
申请日：2014-06-20
Applicant: The Regents of the University of California
Inventor： Arpan Chakraborty , Likun Shen , Umesh K. Mishra
CPC classification number: H01L25/0753 , F21K9/00 , H01L27/156 , H01L33/08 , H01L33/14 , H01L33/20 , H01L33/38 , H01L33/385 , H01L33/42 , H01L33/486 , H01L33/62 , H01L33/64 , H01L2924/0002 , H01L2933/0033 , H01L2933/0066 , H01L2924/00
Abstract: The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.
Abstract translation: 本发明公开了一种排列成阵列的多个交错像素，具有非常低的串联电阻，具有改进的电流扩散和改善的散热。 每个像素是具有尺寸l的边的正方形。 通过增加像素的有源区域的周长来使串联电阻最小化。 串联电阻也通过缩小每个像素的台面和n接触之间的空间来最小化。
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公开(公告)号：US20140299900A1
公开(公告)日：2014-10-09
申请号：US14311071
申请日：2014-06-20
Applicant: The Regents of the University of California
Inventor： Arpan Chakraborty , Likun Shen , Umesh K. Mishra
CPC classification number: H01L25/0753 , F21K9/00 , H01L27/156 , H01L33/08 , H01L33/14 , H01L33/20 , H01L33/38 , H01L33/385 , H01L33/42 , H01L33/486 , H01L33/62 , H01L33/64 , H01L2924/0002 , H01L2933/0033 , H01L2933/0066 , H01L2924/00
Abstract: The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking Each pixel is a square with sides of dimension 1. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.
Abstract translation: 本发明公开了一种排列成阵列的多个交错像素，其具有非常低的串联电阻，并具有改进的电流扩散和改进的散热。每个像素是具有尺寸1侧面的正方形。通过增加周长来使串联电阻最小化 的像素的活动区域。 串联电阻也通过缩小每个像素的台面和n接触之间的空间来最小化。
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