公开(公告)号：US20190088676A1

公开(公告)日：2019-03-21

申请号：US15911369

申请日：2018-03-05

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi TAGAMI ,  Jun IIJIMA ,  Ryota KATSUMATA ,  Kazuyuki HIGASHI

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522

CPC classification number: H01L27/11582 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/26 ,  H01L23/5226 ,  H01L24/04 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

公开(公告)号：US20180240814A1

公开(公告)日：2018-08-23

申请号：US15960842

申请日：2018-04-24

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Masaru KITO ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Hideaki AOCHI

IPC: H01L27/11582 ,  H01L27/11573 ,  G11C16/04

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/1052 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/513

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

公开(公告)号：US20210399004A1

公开(公告)日：2021-12-23

申请号：US17462854

申请日：2021-08-31

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keisuke NAKATSUKA ,  Yoshitaka KUBOTA ,  Tetsuaki UTSUMI ,  Yoshiro SHIMOJO ,  Ryota KATSUMATA

IPC: H01L27/11573 ,  H01L27/11578 ,  H01L27/1157 ,  H01L27/11551 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565

Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.

公开(公告)号：US20200350327A1

公开(公告)日：2020-11-05

申请号：US16932189

申请日：2020-07-17

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoshihiro AKUTSU ,  Ryota KATSUMATA

IPC: H01L27/11556 ,  H01L21/768 ,  H01L21/74 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11578 ,  H01L23/535 ,  H01L27/11573 ,  H01L25/00

Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.

公开(公告)号：US20200212053A1

公开(公告)日：2020-07-02

申请号：US16815852

申请日：2020-03-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tomoo HISHIDA ,  Sadatoshi MURAKAMI ,  Ryota KATSUMATA ,  Masao IWASE

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11575 ,  H01L21/8234

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

公开(公告)号：US20190074284A1

公开(公告)日：2019-03-07

申请号：US16176634

申请日：2018-10-31

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoshihiro AKUTSU ,  Ryota KATSUMATA

IPC: H01L27/11556 ,  H01L25/00 ,  H01L27/11573 ,  H01L27/1157 ,  H01L21/74 ,  H01L21/768 ,  H01L23/535 ,  H01L27/11582 ,  H01L27/11578

CPC classification number: H01L27/11556 ,  H01L21/743 ,  H01L21/76889 ,  H01L23/535 ,  H01L25/00 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of theNAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.

公开(公告)号：US20180358368A1

公开(公告)日：2018-12-13

申请号：US16104843

申请日：2018-08-17

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tomoo HISHIDA ,  Sadatoshi MURAKAMI ,  Ryota KATSUMATA ,  Masao IWASE

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L21/8234 ,  H01L27/11575

CPC classification number: H01L27/1157 ,  H01L21/823437 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.