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11.发明授权Clock data recovery circuit with hybrid second order digital filter having distinct phase and frequency correction latencies 有权具有混合二阶数字滤波器的时钟数据恢复电路具有不同的相位和频率校正延迟公开(公告)号：US08903030B2
公开(公告)日：2014-12-02
申请号：US13670519
申请日：2012-11-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tao Wen Chung , Chan-Hong Chern , Ming-Chieh Huang , Chih-Chang Lin , Yuwen Swei , Tsung-Ching Huang
CPC classification number: H04L7/0331
Abstract: A clock data recovery circuit (CDR) extracts bit data values from a serial bit stream without reference to a transmitter clock. A controllable oscillator produces a regenerated clock signal controlled to match the frequency and phase of transitions between bits and the serial data is sampled at an optimal phase. A phase detector generates early-or-late indication bits for clock versus data transition times, which are accumulated and applied to a second order feedback control with two distinct feedback paths for frequency and phase, combined for correcting the controllable oscillator, selecting a sub-phase and/or determining an optimal phase at which the bit stream data values are sampled. The second order filter is operated at distinct rates such that the phase correction has a latency as short as one clock cycle and the frequency correction latency occurs over plural cycles.
Abstract translation: 时钟数据恢复电路（CDR）从串行比特流中提取比特数据值而不参考发射机时钟。 可控振荡器产生受控的再生时钟信号以匹配位之间的转换的频率和相位，并且在最佳相位对串行数据进行采样。 相位检测器产生用于时钟相对于数据转换时间的早期或晚期指示位，其被积累并应用于具有用于频率和相位的两个不同反馈路径的二阶反馈控制，被组合以校正可控振荡器， 相位和/或确定比特流数据值被采样的最佳相位。 二阶滤波器以不同的速率操作，使得相位校正具有短到一个时钟周期的等待时间，并且频率校正等待时间在多个周期内发生。
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12.发明授权公开(公告)号：US12230636B2
公开(公告)日：2025-02-18
申请号：US18198195
申请日：2023-05-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chan-Hong Chern
IPC: H01L27/095 , H01L21/02 , H01L21/8252 , H01L29/20 , H01L29/205 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/778 , H03K17/16
Abstract: Apparatus and circuits with dual threshold voltage transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first layer comprising a first III-V semiconductor material formed over the substrate; a first transistor formed over the first layer, and a second transistor formed over the first layer. The first transistor comprises a first gate structure comprising a first material, a first source region and a first drain region. The second transistor comprises a second gate structure comprising a second material, a second source region and a second drain region. The first material is different from the second material.
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公开(公告)号：US11860421B2
公开(公告)日：2024-01-02
申请号：US17097270
申请日：2020-11-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Weiwei Song , Chan-Hong Chern , Chewn-Pu Jou , Stefan Rusu , Min-Hsiang Hsu
Abstract: An optical system with different optical coupling device configurations and a method of fabricating the same are disclosed. An optical system includes a substrate, a waveguide disposed on the substrate, an optical fiber optically coupled to the waveguide, and an optical coupling device disposed between the optical fiber and the waveguide. The optical coupling device configured to optically couple the optical fiber to the waveguide. The optical coupling device includes a dielectric layer disposed on the substrate, a semiconductor tapered structure disposed in a first horizontal plane within the dielectric layer, and a multi-tip dielectric structure disposed in a second horizontal plane within the dielectric layer. The first and second horizontal planes are different from each other.
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公开(公告)号：US20230061568A1
公开(公告)日：2023-03-02
申请号：US17461534
申请日：2021-08-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Min-Hsiang Hsu , Chewn-Pu Jou , Chan-Hong Chern , Cheng-Tse Tang , Yung-Jr Hung , Lan-Chou Cho
IPC: G02B6/30
Abstract: Disclosed are edge couplers having a high coupling efficiency and low polarization dependent loss, and methods of making the edge couplers. In one embodiment, a semiconductor device for optical coupling is disclosed. The semiconductor device includes: a substrate; an optical waveguide over the substrate; and a plurality of layers over the optical waveguide. The plurality of layers includes a plurality of coupling pillars disposed at an edge of the semiconductor device. The plurality of coupling pillars form an edge coupler configured for optically coupling the optical waveguide to an optical fiber placed at the edge of the semiconductor device.
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公开(公告)号：US11417596B2
公开(公告)日：2022-08-16
申请号：US16984297
申请日：2020-08-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Weiwei Song , Chan-Hong Chern , Feng-Wei Kuo , Lan-Chou Cho , Stefan Rusu
IPC: H01L23/52 , H01L31/18 , H01L31/0232 , G02B6/43
Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an insulator layer arranged over a substrate. Further, an upper routing structure is arranged over the insulator layer and is made of a semiconductor material. A lower optical routing structure is arranged below the substrate and is embedded in a lower dielectric structure. The integrated chip further includes an anti-reflective layer that is arranged below the substrate and directly contacts the substrate.
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Patent Agency Ranking
公开(公告)号：US11169328B2
公开(公告)日：2021-11-09
申请号：US16919747
申请日：2020-07-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chan-Hong Chern , Min-Hsiang Hsu
Abstract: A photonic structure is provided. The photonic structure includes a semiconductor substrate, a buried oxide layer over the semiconductor substrate, an optical coupling region over the buried oxide layer, and an oxide structure embedded in the semiconductor substrate. The optical coupling region is tapered toward a terminus of the optical coupling region located at an edge of the semiconductor substrate. The optical coupling region overlaps the oxide structure in a plan view.
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17.发明授权公开(公告)号：US10971616B2
公开(公告)日：2021-04-06
申请号：US16576554
申请日：2019-09-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chan-Hong Chern
IPC: H01L29/778 , H01L27/07 , H01L29/66 , H03K17/567
Abstract: Apparatus and circuits with dual polarization transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a first active portion having a first thickness and a second active portion having a second thickness; a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first thickness is different from the second thickness.
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公开(公告)号：US09503252B2
公开(公告)日：2016-11-22
申请号：US14164399
申请日：2014-01-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ming-Chieh Huang , Chan-Hong Chern , Tao Wen (David) Chung , Tsung-Ching (Jim) Huang , Chih-Chang Lin
CPC classification number: H04L7/0025 , H03L7/0812
Abstract: Some embodiments relate to a phase interpolator. The phase interpolator includes a control block to provide a plurality of phase interpolation control signals which are collectively indicative of a phase difference between a first clock and a second clock. The phase interpolation control signals define different phase step sizes by which the first clock is to be phase shifted to limit the phase difference. A plurality of Gilbert cells provide a plurality of current levels, respectively, based on the plurality of phase interpolation control signals. A plurality of current control elements adjust the plurality of current levels from the plurality of Gilbert cells. The plurality of current levels are adjusted by different amounts for the different phase step sizes.
Abstract translation: 一些实施例涉及相位插值器。 相位插值器包括一个控制块，用于提供多个相位插值控制信号，这些相位插值控制信号集中表示第一时钟和第二时钟之间的相位差。 相位插值控制信号限定不同的相位步长，通过该相位步长第一时钟将被相移以限制相位差。 多个吉尔伯特单元基于多个相位插值控制信号分别提供多个电流电平。 多个电流控制元件从多个吉尔伯特单元调整多个电流电平。 对于不同的相位步长，多个电流水平被不同的量调节。
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公开(公告)号：US09391626B2
公开(公告)日：2016-07-12
申请号：US14456064
申请日：2014-08-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin , Tsung-Ching Huang , Fu-Lung Hsueh
CPC classification number: H03L7/103 , H03L7/097 , H03L7/0995 , H03L7/1072 , H03L7/18 , H03L2207/06
Abstract: A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.
Abstract translation: 电路包括电容负载压控振荡器，其具有被配置为接收第一输入信号的输入和被配置为输出振荡输出信号的输出。 校准电路耦合到压控振荡器，并被配置为将一个或多个控制信号输出到电容负载压控振荡器，用于调整振荡输出信号的频率。 校准电路被配置为响应于输入电压与至少一个参考电压的比较而输出一个或多个控制信号。
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公开(公告)号：US12272744B2
公开(公告)日：2025-04-08
申请号：US17571281
申请日：2022-01-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chan-Hong Chern
IPC: H01L29/778 , H01L27/085 , H01L29/205 , H01L29/66
Abstract: Apparatus and circuits including transistors with different polarizations and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a first active portion and a second active portion; a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first active portion has a material composition different from that of the second active portion.
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