公开(公告)号：US11901455B2

公开(公告)日：2024-02-13

申请号：US17813888

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Kuo-Ju Chen ,  Kai-Hsuan Lee ,  I-Hsieh Wong ,  Cheng-Yu Yang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Syun-Ming Jang ,  Meng-Han Chou

IPC: H01L21/266 ,  H01L21/3115 ,  H01L21/764 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/285 ,  H01L21/762 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/49

CPC classification number: H01L29/7851 ,  H01L21/266 ,  H01L21/31155 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/28518 ,  H01L21/76224 ,  H01L21/76843 ,  H01L21/76855 ,  H01L2221/1063

Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

公开(公告)号：US20230052380A1

公开(公告)日：2023-02-16

申请号：US17977405

申请日：2022-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yu Yang ,  Yen-Ting Chen ,  Wei-Yang Lee ,  Fu-Kai Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/033 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate, at least two gate structures disposed over the substrate, each of the at least two gate structures including a gate electrode and a spacer disposed along sidewalls of the gate electrode, wherein the spacer includes a refill portion and a bottom portion, the refill portion of the spacer has a funnel shape such that a top surface of the refill portion of the spacer is larger than a bottom surface of the refill portion of the spacer, and a source/drain contact disposed over the substrate and between the spacers of the at least two gate structures.

公开(公告)号：US20210143069A1

公开(公告)日：2021-05-13

申请号：US17122535

申请日：2020-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yu Yang ,  Yen-Ting Chen ,  Wei-Yang Lee ,  Fu-Kai Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/033 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate, at least two gate structures disposed over the substrate, each of the at least two gate structures including a gate electrode and a spacer disposed along sidewalls of the gate electrode, wherein the spacer includes a refill portion and a bottom portion, the refill portion of the spacer has a funnel shape such that a top surface of the refill portion of the spacer is larger than a bottom surface of the refill portion of the spacer, and a source/drain contact disposed over the substrate and between the spacers of the at least two gate structures.

公开(公告)号：US20190074225A1

公开(公告)日：2019-03-07

申请号：US16181847

申请日：2018-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yu Yang ,  Chia-Ta Yu ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Feng-Cheng Yang

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method includes providing a device structure having a substrate, an isolation structure over the substrate, and two fins extending from the substrate and through the isolation structure, each fin having two source/drain (S/D) regions and a channel region; depositing a first dielectric layer over top and sidewall surfaces of the fins and over the isolation structure; forming a gate stack over the first dielectric layer and engaging each fin at the respective channel region; treating surfaces of the gate stack and the first dielectric layer such that the surfaces of the gate stack are more attachable to a second dielectric layer than the surfaces of the first dielectric layer are; after the treating of the surfaces, depositing the second dielectric layer; and etching the first dielectric layer to expose the S/D regions of the fins.

公开(公告)号：US20210020757A1

公开(公告)日：2021-01-21

申请号：US16511258

申请日：2019-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yu Yang ,  Kai-Hsuan Lee ,  Wei-Yang Lee ,  Fu-Kai Yang ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes a first gate stack, a second gate stack, a first source/drain feature disposed between the first and second gate stacks, and a source/drain contact over and electrically coupled to the first source/drain feature. The source/drain contact is spaced apart from each of the first and second gate stacks by an inner spacer disposed on sidewalls of the source/drain contact, a first air gap, a first gate spacer, and a second air gap separated from the first air gap by the first gate spacer.

公开(公告)号：US10535525B2

公开(公告)日：2020-01-14

申请号：US15692221

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Chun-Hsiung Lin ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Cheng-Yu Yang ,  Yen-Ting Chen

IPC: H01L21/8234 ,  H01L21/285 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/165

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate, a gate structure, a first doped structure, a second doped structure, and a dielectric layer. The method includes forming a through hole in the dielectric layer. The method includes performing a physical vapor deposition process to deposit a first metal layer over the first doped structure exposed by the through hole. The method includes reacting the first metal layer with the first doped structure to form a metal semiconductor compound layer between the first metal layer and the first doped structure. The method includes removing the first metal layer. The method includes performing a chemical vapor deposition process to deposit a second metal layer in the through hole. The method includes forming a conductive structure in the through hole and over the second metal layer.

公开(公告)号：US10283624B1

公开(公告)日：2019-05-07

申请号：US15875485

申请日：2018-01-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Hsuan Lee ,  Bo-Yu Lai ,  Chi-On Chui ,  Cheng-Yu Yang ,  Yen-Ting Chen ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/762 ,  H01L21/306 ,  H01L29/417

Abstract: A semiconductor device and a method for forming the same are provided. The method includes forming a gate structure over a fin structure. The method further includes forming first gate spacers on opposite sidewalls of the gate structure. The method further includes forming source/drain features in the fin structure and adjacent to the first gate spacers. The method further includes performing a surface treatment process on top surfaces of the source/drain features and outer sidewalls of the first gate spacers. The method further includes depositing a contact etch stop layer (CESL) over the source/drain features and the first gate spacers. A first portion of the CESL is deposited over the top surfaces of the source/drain features at a first deposition rate. A second portion of the CESL is deposited over the outer sidewalls of the first gate spacers at a second deposition rate.

公开(公告)号：US10141231B1

公开(公告)日：2018-11-27

申请号：US15688274

申请日：2017-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yu Yang ,  Chia-Ta Yu ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Feng-Cheng Yang

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method includes forming two fins extending from a substrate, each fin having two source/drain (S/D) regions and a channel region; forming a gate stack engaging each fin at the respective channel region; depositing one or more dielectric layers over top and sidewall surfaces of the gate stack and over top and sidewall surfaces of the S/D regions of the fins; and performing an etching process to the one or more dielectric layers. The etching process simultaneously produces a polymer layer over the top surface of the gate stack, resulting in the top and sidewall surfaces of the S/D regions of the fins being exposed and a majority of the sidewall surface of the gate stack still being covered by the one or more dielectric layers. The method further includes growing one or more epitaxial layers over the top and sidewall surfaces of the S/D regions of the fins.

公开(公告)号：US09997631B2

公开(公告)日：2018-06-12

申请号：US15226321

申请日：2016-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yu Yang ,  Kai-Hsuan Lee ,  Sheng-Chen Wang ,  Sai-Hooi Yeong ,  Yi-Fang Pai ,  Yen-Ming Chen

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L21/311 ,  H01L29/04 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/31111 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of forming a semiconductor device includes forming a fin on a substrate and forming a source/drain region on the fin. The method further includes forming a doped metal silicide layer on the source/drain region and forming a super-saturated doped interface between the doped metal silicide and the source/drain region. An example benefit includes reduction of contact resistance between metal silicide layers and source/drain regions.

公开(公告)号：US09865595B1

公开(公告)日：2018-01-09

申请号：US15490959

申请日：2017-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Yu ,  Sheng-Chen Wang ,  Cheng-Yu Yang ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/00 ,  H01L21/338 ,  H01L21/337 ,  H01L29/768 ,  H01L29/80 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847

Abstract: A FinFET device is provided. The FinFET device includes a plurality of fin structures that protrude upwardly out of a dielectric isolation structure. The FinFET device also includes a plurality of gate structures that partially wrap around the fin structures. The fin structures each extend in a first direction, and the gate structures each extend in a second direction different from the first direction. An epitaxial structure is formed over at least a side surface of each of the fin structures. The epitaxial structure includes: a first epi-layer, a second epi-layer, or a third epi-layer. The epitaxial structure formed over each fin structure is separated from adjacent epitaxial structures by a gap. A silicide layer is formed over each of the epitaxial structures. The silicide layer at least partially fills in the gap. Conductive contacts are formed over the silicide layer.