公开(公告)号：US10297631B2

公开(公告)日：2019-05-21

申请号：US15213519

申请日：2016-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ying Ho ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yan-Chih Lu

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) structure having a conductive blocking structure configured prevent radiation produced by a device within a first die from affecting an image sensing element within a second die. The IC structure has a first IC die with one or more semiconductor devices and a second IC die with an array of image sensing elements. A hybrid bonding interface region is arranged between the first and second IC die. A conductive bonding structure is arranged within the hybrid bonding interface region and is configured to electrically couple the first IC die to the second IC die. A conductive blocking structure is arranged within the hybrid bonding interface region and extends laterally between the one or more semiconductor devices and the array of image sensing elements.

公开(公告)号：US10283549B2

公开(公告)日：2019-05-07

申请号：US16046183

申请日：2018-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung

IPC: H01L27/146

Abstract: Some embodiments of the present disclosure relate to a method of forming an integrated chip. The method includes forming a first interconnect wire within a first inter-level dielectric (ILD) layer over a substrate. One or more vias are formed on the first interconnect wire and within a second ILD layer separated from the substrate by the first ILD layer. One or more additional vias are formed within the second ILD layer. Respective ones of the one or more vias have a larger size than respective ones of the one or more additional vias. A thickness of the substrate is reduced, and the substrate is etched to form a bond pad opening extending through the substrate to the first interconnect wire. A bond pad is formed within the bond pad opening and directly over the one or more vias.

公开(公告)号：US10269840B2

公开(公告)日：2019-04-23

申请号：US15487593

申请日：2017-04-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Feng-Chi Hung ,  Jen-Cheng Liu ,  Ching-Chun Wang ,  Tse-Hua Lu

IPC: H04N3/14 ,  H04N5/335 ,  H04N9/04 ,  H04N5/225 ,  H01L31/062 ,  H01L31/113 ,  H01L27/146

Abstract: The image sensing device includes a pixel region in a pixel array area and a dummy pixel region in a periphery area. The pixel region includes a radiation region, a floating diffusion region, a transfer transistor, a source-follower transistor, a reset transistor and a select transistor. The dummy pixel region includes a radiation region and a floating diffusion region. A gate of one of the transfer transistor, the reset transistor and the select transistor in the pixel region is electrically connected to the radiation region or the floating diffusion region in the dummy pixel region.

公开(公告)号：US20190057998A1

公开(公告)日：2019-02-21

申请号：US16167844

申请日：2018-10-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/14689

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a substrate and a first interconnect wire arranged within a dielectric structure on the substrate. A bond pad contacts the first interconnect wire. A via support structure has one or more vias arranged within the dielectric structure at a location separated from the substrate by the first interconnect wire, The via support structure has a metal pattern density that is greater than or equal to approximately 19% and that is configured to mitigate damage caused by a force of a bonding process on the bond pad.

公开(公告)号：US20180204862A1

公开(公告)日：2018-07-19

申请号：US15919784

申请日：2018-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Tzu-Jui Wang ,  Yen-Ting Chiang ,  Yu-Jen Wang ,  Yuichiro Yamashita

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689

Abstract: The present disclosure, in some embodiments, relates to a CMOS image sensor. The CMOS image sensor has an image sensing element disposed within a substrate. A plurality of isolation structures are arranged along a back-side of the substrate and are separated from opposing sides of the image sensing element by non-zero distances. A doped region is laterally arranged between the plurality of isolation structures. The doped region is also vertically arranged between the image sensing element and the back-side of the substrate. The doped region physically contacts the image sensing element.

公开(公告)号：US20170309675A1

公开(公告)日：2017-10-26

申请号：US15647968

申请日：2017-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Min Lin ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Chun-Ming Su ,  Tzu-Hsuan Hsu

IPC: H01L27/146 ,  H04N9/04

CPC classification number: H01L27/14685 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14643 ,  H04N9/045

Abstract: A device includes a semiconductor substrate, a plurality of micro-lenses disposed on the substrate, each micro-lens being configured to direct light radiation to a layer beneath the plurality of micro-lenses. The device further includes a transparent layer positioned between the plurality of micro-lenses and the substrate, the transparent layer comprising a structure that is configured to block light radiation that is traveling towards a region between adjacent micro-lenses, wherein the structure and the transparent material are coplanar at respective top surfaces and bottom surfaces thereof.

公开(公告)号：US20170221950A1

公开(公告)日：2017-08-03

申请号：US15213519

申请日：2016-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ying Ho ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yan-Chih Lu

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469 ,  H01L2224/05 ,  H01L2224/48451

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) structure having a conductive blocking structure configured prevent radiation produced by a device within a first die from affecting an image sensing element within a second die. The IC structure has a first IC die with one or more semiconductor devices and a second IC die with an array of image sensing elements. A hybrid bonding interface region is arranged between the first and second IC die. A conductive bonding structure is arranged within the hybrid bonding interface region and is configured to electrically couple the first IC die to the second IC die. A conductive blocking structure is arranged within the hybrid bonding interface region and extends laterally between the one or more semiconductor devices and the array of image sensing elements.

公开(公告)号：US09679939B1

公开(公告)日：2017-06-13

申请号：US15207727

申请日：2016-07-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yun-Wei Cheng ,  Yin-Chieh Huang ,  Ching-Chun Wang ,  Chun-Hao Chou ,  Kuo-Cheng Lee ,  Hsun-Ying Huang

IPC: H01L21/00 ,  H01L27/146

CPC classification number: H01L27/1464 ,  H01L27/14607 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14643

Abstract: A backside illuminated (BSI) image sensor device includes a device layer, a doped isolation region and a doped radiation sensing region. The device layer has a front side and a backside, in which the device layer has a thickness greater than or equal to 4 μm. The doped isolation region having a first dopant of a first conductivity is through the device layer to define a plurality of pixel regions of the device layer, in which the doped isolation region includes a first upper region adjacent to the front side and a first lower region between the first upper region and the backside, and the first upper region has a width less than a width of the first lower region. The doped radiation sensing region having a second dopant of a second conductivity opposite to the first conductivity is in one of the pixel regions of the device layer.

公开(公告)号：US20170117316A1

公开(公告)日：2017-04-27

申请号：US15149561

申请日：2016-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chun Hsu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Jeng-Shyan Lin ,  Shyh-Fann Ting

IPC: H01L27/146 ,  H01L23/00

Abstract: The present disclosure relates to an integrated circuit having a bond pad with a relatively flat surface topography that mitigates damage to underlying layers. In some embodiments, the integrated circuit has a plurality of metal interconnect layers within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has a recess with sidewalls connecting a horizontal surface of the passivation structure to an upper surface of the passivation structure. A bond pad is arranged within the recess and has a lower surface overlying the horizontal surface. One or more protrusions extend outward from the lower surface through openings in the passivation structure to contact one of the metal interconnect layers. Arranging the bond pad within the recess and over the passivation structure mitigates stress to underlying layers during bonding without negatively impacting an efficiency of an image sensing element within the substrate.

公开(公告)号：US11322481B2

公开(公告)日：2022-05-03

申请号：US16902539

申请日：2020-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao ,  Yung-Lung Lin ,  Shih-Han Huang ,  I-Nan Chen

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/48 ,  H01L23/532 ,  H01L25/00 ,  H01L23/00

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. A third IC die is bonded to the second IC die by a second bonding structure. The second bonding structure is arranged between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. The second bonding structure further comprises conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.