公开(公告)号：US20220367632A1

公开(公告)日：2022-11-17

申请号：US17872452

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L29/08 ,  H01L29/167 ,  H01L29/78 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L21/265 ,  H01L29/417

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US20190288068A1

公开(公告)日：2019-09-19

申请号：US16433374

申请日：2019-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Maio Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L29/08 ,  H01L21/265 ,  H01L21/02 ,  H01L29/66 ,  H01L29/167 ,  H01L29/78 ,  H01L21/285

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US10347720B2

公开(公告)日：2019-07-09

申请号：US15797703

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L21/02 ,  H01L29/08 ,  H01L29/167 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66 ,  H01L21/265

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US20180349545A1

公开(公告)日：2018-12-06

申请号：US16059367

申请日：2018-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Ming-Hui Chih ,  Ping-Chieh Wu ,  Chun-Hung Wu ,  Wen-Hao Liu ,  Cheng-Hsuan Huang ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5081 ,  G03F1/36

Abstract: The present disclosure relates to a method of data preparation. The method, in some embodiments, performs a first data preparation process using a data preparation element. The first data preparation process modifies a plurality of shapes of an integrated chip (IC) design that comprises a graphical representation of a layout used to fabricate an integrated chip. A plurality of additional shapes are added to the IC design using an additional shape insertion element. The plurality of additional shapes are separated from the plurality of shapes by one or more non-zero distances. A second data preparation process is performed using the data preparation element, after performing the first data preparation process. The second data preparation process modifies the plurality of additional shapes.

公开(公告)号：US20160275232A1

公开(公告)日：2016-09-22

申请号：US15170026

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Ming-Hui Chih ,  Ping-Chieh Wu ,  Chun-Hung Wu ,  Wen-Hao Liu ,  Cheng-Hsuan Huang ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5081 ,  G03F1/36

Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by performing an initial data preparation process on an IC design including a graphical representation of a layout used to fabricate an integrated chip. The initial data preparation process is performed by using a data preparation element to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design. One or more low-pattern-density areas of the modified IC design are identified using a local density checking element. One or more dummy shapes are added within the one or more low-pattern-density areas using a dummy shape insertion element. The one or more dummy shapes are separated from the modified shapes by a non-zero space.

Abstract translation: 本公开涉及一种利用低OPC（光学邻近校正）周期时间改进图案密度的方法，以及相关联的装置。 在一些实施例中，通过对包括用于制造集成芯片的布局的图形表示的IC设计执行初始数据准备处理来执行该方法。 通过使用数据准备元件来进行初始数据准备处理，以生成具有改进形状的修改的IC设计，其是IC设计中的形状的修改形式。 使用局部密度检查元件来识别修改的IC设计的一个或多个低图案密度区域。 使用虚拟形状插入元件在一个或多个低图案密度区域内添加一个或多个虚拟形状。 一个或多个虚拟形状通过非零空间与修改后的形状分离。

公开(公告)号：US20240379751A1

公开(公告)日：2024-11-14

申请号：US18781098

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Chun-Hung Wu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes depositing a multi-layer stack on a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a dummy gate on the multi-layer stack; forming a first spacer on a sidewall of the dummy gate; performing a first implantation process to form a first doped region, the first implantation process having a first implant energy and a first implant dose; performing a second implantation process to form a second doped region, where the first doped region and the second doped region are in a portion of the channel layers uncovered by the first spacer and the dummy gate, the second implantation process having a second implant energy and a second implant dose, where the second implant energy is greater than the first implant energy, and where the first implant dose is different from the second implant dose.

公开(公告)号：US12087578B2

公开(公告)日：2024-09-10

申请号：US17651851

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hung Wu ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/0273 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method of forming a semiconductor device includes forming a photoresist over a target layer, where the target layer includes a substrate. The photoresist is patterned to form a patterned photoresist. Scum remains between portions of the patterned photoresist. The substrate is tilted relative to a direction of propagation of an ion beam. An ion treatment is performed on the scum. A pattern of the patterned photoresist is transferred to the target layer.

公开(公告)号：US12015055B2

公开(公告)日：2024-06-18

申请号：US18350838

申请日：2023-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L29/167 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/28518 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US20230352533A1

公开(公告)日：2023-11-02

申请号：US18350838

申请日：2023-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L21/02 ,  H01L21/265 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L29/167 ,  H01L21/285

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/28518 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US20220406592A1

公开(公告)日：2022-12-22

申请号：US17651851

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hung Wu ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/3213

Abstract: A method of forming a semiconductor device includes forming a photoresist over a target layer, where the target layer includes a substrate. The photoresist is patterned to form a patterned photoresist. Scum remains between portions of the patterned photoresist. The substrate is tilted relative to a direction of propagation of an ion beam. An ion treatment is performed on the scum. A pattern of the patterned photoresist is transferred to the target layer.