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    PHASE-LOCKED LOOP CIRCUIT
    11.
    发明申请
    PHASE-LOCKED LOOP CIRCUIT 有权
    相位锁定环路

    公开(公告)号：US20150116018A1

    公开(公告)日：2015-04-30

    申请号：US14320168

    申请日：2014-06-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Huan-Neng CHEN ,  Kuang-Kai YEN ,  Feng-Wei KUO ,  Hsien-Yuan LIAO ,  Tsung-Hsiung LEE ,  Chewn-Pu JOU ,  Robert Bogdan STASZEWSKI

    IPC: H03L7/091 ,  H03L7/099 ,  H03L7/093

    CPC classification number: H03L7/091 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0991 ,  H03L2207/50

    Abstract: A phase-locked loop circuit, a phase converter module thereof and a phase-locked controlling method are disclosed herein. The phase converter module is suitable for a phase-locked loop circuit including a digitally-controlled oscillator (DCO) for generating an oscillator output signal and a divider for converting the oscillator output signal into N-phased oscillator output signals. The phase converter module includes a period extender, a phase finder and a time-to-digital converter. The period extender is configured for extending the N-phased oscillator output signals into M*N-phased oscillator output signals corresponding to M oscillation period of the digitally-controlled oscillator. The phase finder is configured for sampling the oscillator output signal with the M*N-phased oscillator output signals to calculate an estimated value of the fractional phase part. The time-to-digital converter is configured to calculate a precise value of the fractional phase part within one sub-period.

    Abstract translation: 本文公开了一种锁相环电路，其相变转换器模块和锁相控制方法。 相位转换器模块适用于包括用于产生振荡器输出信号的数字控制振荡器（DCO）和用于将振荡器输出信号转换成N相振荡器输出信号的分频器的锁相环电路。 相位转换器模块包括周期延长器，相位取样器和时间 - 数字转换器。 周期延长器被配置为将N相振荡器输出信号扩展到对应于数字控制振荡器的M个振荡周期的M * N个相位振荡器输出信号。 相位器被配置为用M * N相位振荡器输出信号对振荡器输出信号进行采样，以计算分数阶段的估计值。 时间 - 数字转换器被配置为计算一个子周期内的分数阶段的精确值。

    ALL-DIGITAL PHASE LOCKED LOOP USING SWITCHED CAPACITOR VOLTAGE DOUBLER
    14.
    发明申请
    ALL-DIGITAL PHASE LOCKED LOOP USING SWITCHED CAPACITOR VOLTAGE DOUBLER 审中-公开

    公开(公告)号：US20190288692A1

    公开(公告)日：2019-09-19

    申请号：US16429774

    申请日：2019-06-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Feng Wei KUO ,  Chewn-Pu JOU ,  Huan-Neng CHEN ,  Lan-Chou CHO ,  Robert Bogdan STASZEWSKI ,  Seyednaser POURMOUSAVIAN

    IPC: H03L1/00 ,  H03L7/099 ,  H03L7/093 ,  H03L7/08

    Abstract: An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations. The digital circuitry regulates the digital input supply voltage to stabilize the resolution of the TDC across the PVT variations. This stabilization of the resolution of the TDC can cause the ADPLL to maintain a fixed in-band phase noise across the PVT variations.

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