公开(公告)号：US20210167018A1

公开(公告)日：2021-06-03

申请号：US17176299

申请日：2021-02-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L23/31 ,  H01L23/14 ,  H01L25/065

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

公开(公告)号：US20210057383A1

公开(公告)日：2021-02-25

申请号：US17094161

申请日：2020-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Wei Lu ,  Ying-Da Wang ,  Li-Chung Kuo ,  Jing-Cheng Lin

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/78

Abstract: A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.

公开(公告)号：US10804247B2

公开(公告)日：2020-10-13

申请号：US16159816

申请日：2018-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L23/60 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L25/10 ,  H01L21/78 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film is electrically connected to the first ground bump.

公开(公告)号：US20200035622A1

公开(公告)日：2020-01-30

申请号：US16595741

申请日：2019-10-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/14 ,  H01L23/48 ,  H01L23/498

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure has a first conductive layer on a first substrate and a second conductive layer on a second substrate. A bonding structure is disposed between the first conductive layer and the second conductive layer. A support structure is disposed between the first substrate and the second substrate. A passivation layer covers a bottom surface of the first conductive layer and has a lower surface facing an uppermost surface of the support structure.

公开(公告)号：US10535627B2

公开(公告)日：2020-01-14

申请号：US16218495

申请日：2018-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Li-Hui Cheng ,  Po-Hao Tsai ,  Chih-Chien Pan

IPC: H01L21/00 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L21/67 ,  H01L25/00 ,  H01L21/683

Abstract: A printing module, printing method and system of forming a printed structure are provided. The printing module includes a first printing dispenser operable to dispense a first material, a second printing dispenser operable to dispense a second material, a first curing unit, a second curing unit and a third curing unit. The first, the second and the third curing units each is operable to irradiate a light capable of curing the first and second materials and are alternately arranged with the first and second printing dispensers along a line. The first and second printing dispensers and the first, second and third curing units are simultaneously movable along the line. During the second curing unit and one of the first curing unit and the third curing unit are operable to irradiate the light, the other of the first curing unit and the third curing unit is off.

公开(公告)号：US20200006196A1

公开(公告)日：2020-01-02

申请号：US16431747

申请日：2019-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Szu-Wei Lu

IPC: H01L23/433 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L25/10 ,  H01L25/18 ,  H01L23/31

Abstract: Semiconductor packages are provided. One of the semiconductor package includes a semiconductor die, a thermal conductive pattern, an encapsulant and a thermal conductive layer. The thermal conductive pattern is disposed aside the semiconductor die. The encapsulant encapsulates the semiconductor die and the thermal conductive pattern. The thermal conductive layer covers a rear surface of the semiconductor die, wherein the thermal conductive pattern is thermally coupled to the semiconductor die through the thermal conductive layer and electrically insulated from the semiconductor die.

公开(公告)号：US20190043849A1

公开(公告)日：2019-02-07

申请号：US16158244

申请日：2018-10-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hui Cheng ,  Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process.

公开(公告)号：US10163813B2

公开(公告)日：2018-12-25

申请号：US15354195

申请日：2016-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31

Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure and a grounding line in the dielectric structure. The grounding line includes a main portion and an end enlarged portion connected to the main portion and laterally accessible from the dielectric structure. The chip package structure includes a chip structure over the redistribution structure. The chip package structure includes a conductive shielding film disposed over the chip structure and a first sidewall of the end enlarged portion. The conductive shielding film is electrically connected to the grounding line. A thickness of the end enlarged portion increases from the main portion to the conductive shielding film.

公开(公告)号：US09929128B1

公开(公告)日：2018-03-27

申请号：US15492617

申请日：2017-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hui Cheng ,  Po-Hao Tsai ,  Jing-Cheng Lin ,  Yi-Hang Lin

IPC: H01L23/48 ,  H01L25/10 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/32 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/0105 ,  H01L2924/14

Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure. The chip package structure includes a first chip over the redistribution structure. The first chip has a front surface and a back surface opposite to the front surface, and the front surface faces the redistribution structure. The chip package structure includes an adhesive layer on the back surface. The adhesive layer is in direct contact with the back surface, and a first maximum length of the adhesive layer is less than a second maximum length of the first chip. The chip package structure includes a molding compound layer over the redistribution structure and surrounding the first chip and the adhesive layer. A first top surface of the adhesive layer is substantially coplanar with a second top surface of the molding compound layer.

公开(公告)号：US09859112B2

公开(公告)日：2018-01-02

申请号：US13945217

申请日：2013-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., LTD.

Inventor： Jing-Cheng Lin

IPC: H01L21/30 ,  H01L21/02 ,  H01L27/06 ,  H01L21/822 ,  H01L21/20 ,  H01L23/48 ,  H01L21/762

CPC classification number: H01L21/02104 ,  H01L21/2007 ,  H01L21/76254 ,  H01L21/8221 ,  H01L23/481 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method is disclosed that includes the steps outlined below. An epitaxial layer is formed on a first semiconductor substrate. At least one implant species is implanted between the epitaxial layer and the first semiconductor substrate to form an ion-implanted layer. The epitaxial layer is bonded to a bonding oxide layer of a second semiconductor substrate. The first semiconductor substrate is separated from the ion-implanted layer.