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    SYSTEM AND METHOD FOR VALIDATING STACKED DIES BY COMPARING CONNECTIONS
    11.
    发明申请
    SYSTEM AND METHOD FOR VALIDATING STACKED DIES BY COMPARING CONNECTIONS 审中-公开
    通过比较连接来确认堆叠式柴油机的系统和方法

    公开(公告)号：US20150234979A1

    公开(公告)日：2015-08-20

    申请号：US14705021

    申请日：2015-05-06

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Ashok MEHTA ,  Stanley JOHN ,  Kai-Yuan TING ,  Sandeep Kumar GOEL ,  Chao-Yang YEH

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/50 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/78

    Abstract: A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.

    Abstract translation: 一种系统包括被配置为产生集成电路（IC）裸片的布局的由处理器实现的工具。 至少一个非暂时机器可读存储介质包括分别由第一和第二集成电路（IC）管芯上形成的第一和第二电路图案的第一栅极级描述编码的第一部分，以及用第 从处理器实现的工具接收的第一和第二电路图案的第二门级描述。 第二门级描述包括电源和接地端口，并且第一门级描述不包括电源和接地端口。 提供了一种处理器实现的第一验证模块，用于比较第一和第二门级描述并输出第一和第二电路图案的经验证的第二门级描述。

    SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION OF MULTI-DIE 3D ICs
    12.
    发明申请
    SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION OF MULTI-DIE 3D ICs 有权
    用于多模3D IC功能验证的系统和方法

    公开(公告)号：US20150123699A1

    公开(公告)日：2015-05-07

    申请号：US14595251

    申请日：2015-01-13

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Stanley JOHN ,  Ashok MEHTA ,  Sandeep Kumar GOEL ,  Kai-Yuan TING

    IPC: G01R31/28

    CPC classification number: G01R31/2886 ,  G01R31/318513

    Abstract: A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.

    Abstract translation: 公开了一种用于多芯片3D IC的功能验证的系统和方法。 该系统和方法包括可复用的验证环境，用于单独地对一堆模具中的每个模具进行测试，而不必同时操作堆叠中的所有模具。 该系统和方法包括将来自芯片验证测试的输入/输出（“IO”）跟踪从第一格式转换为第二格式以提高性能。

    STACKED DIE INTERCONNECT VALIDATION
    13.
    发明申请
    STACKED DIE INTERCONNECT VALIDATION 审中-公开
    堆叠DIE互连验证

    公开(公告)号：US20130167095A1

    公开(公告)日：2013-06-27

    申请号：US13770158

    申请日：2013-02-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ashok MEHTA ,  Stanley JOHN ,  Kai-Yuan TING ,  Sandeep Kumar GOEL ,  Chao-Yang YEH

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/50 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/78

    Abstract: A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.

    Abstract translation: 一种系统包括被配置为产生集成电路（IC）裸片的布局的由处理器实现的工具。 至少一个非暂时机器可读存储介质包括分别由第一和第二集成电路（IC）管芯上形成的第一和第二电路图案的第一栅极级描述编码的第一部分，以及用第 从处理器实现的工具接收的第一和第二电路图案的第二门级描述。 第二门级描述包括电源和接地端口，并且第一门级描述不包括电源和接地端口。 提供了一种处理器实现的第一验证模块，用于比较第一和第二门级描述并输出第一和第二电路图案的经验证的第二门级描述。

    DEVICE WITH SELF-AUTHENTICATION
    14.
    发明公开
    DEVICE WITH SELF-AUTHENTICATION 审中-公开

    公开(公告)号：US20240022427A1

    公开(公告)日：2024-01-18

    申请号：US18476019

    申请日：2023-09-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Haohua ZHOU ,  Sandeep Kumar GOEL

    IPC: H04L9/32 ,  H04L9/08

    CPC classification number: H04L9/3239 ,  H04L9/3278 ,  H04L9/0869 ,  H04L2209/805

    Abstract: A device is disclosed. The device includes a first memory circuit and a processing circuit. The first memory circuit stores identifications of the device that are used to generate first hash data through a hash algorithm. The processing circuit is coupled to the first memory circuit and selects at least one bit of each of the identifications in sequence to form a bit sequence, generates second hash data through the hash algorithm based on the bit sequence and authenticates the device according to a comparison between the first hash data and the second hash data.

    PHASE-LOCKED LOOP MONITOR CIRCUIT
    15.
    发明申请
    PHASE-LOCKED LOOP MONITOR CIRCUIT 审中-公开

    公开(公告)号：US20190229737A1

    公开(公告)日：2019-07-25

    申请号：US16372706

    申请日：2019-04-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sandeep Kumar GOEL ,  Ji-Jan Chen ,  Stanley John ,  Yun-Han Lee ,  Yen-Hao Huang

    IPC: H03L7/23 ,  H03L7/095 ,  H03L7/091

    CPC classification number: H03L7/23 ,  H03K19/21 ,  H03L7/091 ,  H03L7/095

    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.

    METHOD AND APPARATUS FOR INTERCONNECT TEST
    17.
    发明申请
    METHOD AND APPARATUS FOR INTERCONNECT TEST 审中-公开
    用于互连测试的方法和装置

    公开(公告)号：US20160259006A1

    公开(公告)日：2016-09-08

    申请号：US15156140

    申请日：2016-05-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sandeep Kumar GOEL ,  Saman M.I. ADHAM

    IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/28

    CPC classification number: G01R31/31717 ,  G01R31/2856 ,  G01R31/3177 ,  G11C29/50

    Abstract: A test circuitry for testing an interconnection between interconnected dies includes a cell embedded within one of the dies. The cell includes a selection logic module that includes a first multiplexer configured to receive a first control signal and provide a first output test signal, and a second multiplexer configured to receive a second control signal and provide a second output test signal. The cell includes a scannable data storage module coupled to the first multiplexer; and a transition generation module configured to receive a third control signal; wherein the first and second output test signals are generated based on respective states of the first, second, and third control signals, and wherein the test circuitry is configured to use the first and second output test signals to perform at least two of: a DC test on the interconnection, an AC test on the interconnection, and a burn-in-test on the interconnection.

    Abstract translation: 用于测试相互连接的管芯之间的互连的测试电路包括嵌入在一个管芯内的电池。 小区包括选择逻辑模块，其包括被配置为接收第一控制信号并提供第一输出测试信号的第一多路复用器，以及被配置为接收第二控制信号并提供第二输出测试信号的第二多路复用器。 该小区包括耦合到第一多路复用器的可扫描数据存储模块; 以及转换生成模块，被配置为接收第三控制信号; 其中所述第一和第二输出测试信号是基于所述第一，第二和第三控制信号的相应状态生成的，并且其中所述测试电路被配置为使用所述第一和第二输出测试信号来执行以下至少两个：DC 互连测试，互连交流测试和互连上的老化测试。

    DEVICE WITH SELF-AUTHENTICATION
    20.
    发明申请
    DEVICE WITH SELF-AUTHENTICATION 有权

    公开(公告)号：US20210218577A1

    公开(公告)日：2021-07-15

    申请号：US17213014

    申请日：2021-03-25

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Haohua ZHOU ,  Sandeep Kumar GOEL

    IPC: H04L9/32 ,  H04L9/08

    Abstract: A device includes a first memory circuit and a processing circuit. The first memory circuit is configured to store first hash data. The processing circuit is coupled to the first memory circuit. The processing circuit is configured to: at least based on a volume of the device, define a size of a distinguishable identification (ID) and a size of second hash data; based on a combination of at least one bit of each of the distinguishable ID and IDs of the device, generate the second hash data; and compare the first hash data with the second hash data, in order to identify whether the device is tampered. A method is also discloses herein.

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