公开(公告)号：US20190333769A1

公开(公告)日：2019-10-31

申请号：US15965635

申请日：2018-04-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yen-Yu CHEN ,  Yu-Chi LU ,  Chih-Pin TSAO ,  Shih-Hsun CHANG

IPC分类号： H01L21/28 ,  H01L29/49

摘要： A method is provided. The method includes the following operations. A dielectric layer is deposited over a substrate. Then, a first work function metal layer is deposited over the dielectric layer. Next, a dummy layer is deposited over the first work function metal layer. Afterwards, an impurity is introduced into the first work function metal layer. Then, the dummy layer is etched. Next, a second work function metal layer is deposited over the first work function metal layer.

公开(公告)号：US20190259760A1

公开(公告)日：2019-08-22

申请号：US16398142

申请日：2019-04-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chia-Chun LIAO ,  Chun-Sheng LIANG ,  Shu-Hui WANG ,  Shih-Hsun CHANG ,  Yi-Jen CHEN

IPC分类号： H01L27/092 ,  H01L29/49 ,  H01L21/8238

摘要： A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.

公开(公告)号：US20180019242A1

公开(公告)日：2018-01-18

申请号：US15211871

申请日：2016-07-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chia-Chun LIAO ,  Chun-Sheng LIANG ,  Shu-Hui WANG ,  Shih-Hsun CHANG ,  Yi-Jen CHEN

IPC分类号： H01L27/092 ,  H01L29/51 ,  H01L21/321 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/49

CPC分类号： H01L27/0924 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

摘要： A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.

公开(公告)号：US20170345721A1

公开(公告)日：2017-11-30

申请号：US15167010

申请日：2016-05-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Heng TSAI ,  Chun-Sheng LIANG ,  Pei-Lin WU ,  Yi-Ren CHEN ,  Shih-Hsun CHANG

IPC分类号： H01L21/8238 ,  H01L29/267 ,  H01L29/24 ,  H01L29/161 ,  H01L29/16 ,  H01L29/08 ,  H01L27/092 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L21/823814 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/7848 ,  H01L29/785

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack has a first upper portion and a first lower portion, and the first upper portion is wider than the first lower portion. The semiconductor device structure includes a spacer layer surrounding the gate stack. The spacer layer has a second upper portion and a second lower portion. The second upper portion is thinner than the second lower portion.

公开(公告)号：US20160359043A1

公开(公告)日：2016-12-08

申请号：US14730210

申请日：2015-06-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yi-Jen CHEN ,  CHIA-CHUN Liao ,  Chun-Sheng LIANG ,  Shih-Hsun CHANG ,  Jen-Hsiang LU

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L29/165 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L29/7851 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7849

摘要： A method of manufacturing a semiconductor Fin FET includes forming a fin structure over a substrate. The fin structure includes an upper layer, part of which is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. A source and a drain are formed. The dummy gate electrode is removed so that the upper layer covered by the dummy gate dielectric layer is exposed. The upper layer of the fin structure is removed to make a recess formed by the dummy gate dielectric layer. Part of the upper layer remains at a bottom of the recess. A channel layer is formed in the recess. The dummy gate dielectric layer is removed. A gate structure is formed over the channel layer.

摘要翻译： 制造半导体Fin FET的方法包括在衬底上形成翅片结构。 翅片结构包括上层，其一部分从隔离绝缘层露出。 在鳍部结构的一部分上形成虚拟栅极结构。 虚拟栅极结构包括伪栅极电极层和伪栅极电介质层。 形成源极和漏极。 去除虚拟栅极电极，使得由虚拟栅极介电层覆盖的上层被暴露。 去除翅片结构的上层以形成由虚拟栅极电介质层形成的凹部。 上层的一部分保留在凹部的底部。 在凹部中形成沟道层。 去除虚拟栅介质层。 在沟道层上形成栅极结构。

公开(公告)号：US20160351563A1

公开(公告)日：2016-12-01

申请号：US14724676

申请日：2015-05-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yi-Jen CHEN ,  Chun-Sheng LIANG ,  Shu-Hui WANG ,  Shih-Hsun CHANG ,  Hsin-Che CHIANG

IPC分类号： H01L27/088 ,  H01L29/49 ,  H01L29/51 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423

CPC分类号： H01L27/088 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/42372 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518

摘要： A process of manufacturing a semiconductor structure is provided. The process begins with forming a work function metal layer on a substrate, and a hardmask is covered over the work function metal layer. A trench is formed to penetrate the hardmask and the work function metal layer, and an isolation structure is filled in the trench.

摘要翻译： 提供一种制造半导体结构的工艺。 该过程开始于在基底上形成功函数金属层，并且硬掩模覆盖在功函数金属层上。 形成沟槽以穿透硬掩模和功函数金属层，并且隔离结构填充在沟槽中。